As the proportion of LWR/CDU in the EPE budget has tightened in recent years, its reduction has become a critical issue. Among many factors, contributions of resist and speckle play a key role in LWR/CDU. The authors therefore carried out a series of experiments in which the resist compositions and the speckle were controlled in order to validate the above points. The spatial frequency of the speckle was controlled by controlling the illumination conditions of the scanner in the experiments. The experiments not only clarified the contributions of resist and speckle, but also confirmed the contribution of the interaction between resist and speckle. We were able to use PSD analysis with the results of a simplified model-based Monte Carlo simulation to explain the interaction between resist and speckle. In addition, experimental results proved that LWR/CDU reduction can be achieved by reducing speckle and optimizing resist composition.
With the advancement of semiconductor device miniaturization, the critical dimension (CD) has reached several tens of nanometers. To meet high yield demands, strict CD control is crucial. However, conventional CD measurement methods such as SEM and scatterometry have a problem; the measurement time increases in proportion to the number of measurement points. To solve this problem, we have developed a CD measurement technology that enables high density measurement of more than 100,000 points on the wafer surface in a few minutes per wafer.1 The CD value is calculated from the correlation between the diffracted light signal and CD. Despite the advantages this method provides, there still have been challenges. Measuring the critical dimensions of resist patterns of several tens of nanometers formed in EUV lithography across the entire wafer sometimes poses difficulties due to insufficient sensitivity with diffracted light, making high-precision CD measurement difficult. In this paper, we propose an enhanced measurement technique that quantifies the changes in the polarization state of diffracted light and reflected light from the wafer as Stokes parameters and calculates the CD based on the correlation between the obtained Stokes parameters and the CD value. Theoretically, it is sensitive to resist patterns of a few nanometers. For accuracy verification, we measured next-generation DRAM process wafers, including EUV-processed wafers. The minimum of measurement error, which compared with the CD value measured by SEM, achieved to 3σ = 0.57. The total time for wafer measurement and calculation processing was about a few minutes per wafer for over 10,000 points on the wafer surface.
In recent years, the number of manufacturing processes is increasing in pursuit of device pattern miniaturization. Complicated processes such as SAQP have been introduced, increasing the number of control parameters. Nevertheless, the demand for production yield enhancement is as high as ever. To detect CD changes, fixed-point measurement by using CD-SEM or scatterometry tools is typically performed, but these time-consuming measurement methods are not suitable for high-density, across-a-wafer measurement or for detecting CD anomalies that randomly occur. To address these issues, we have developed a technology that enables high-precision CD measurement of more than 100,000 points per wafer within a few minutes. It enables monitoring various CD defects in various processes such as holes and L/S patterns after photolithography, L/S patterns after SAQP/SADP, and fine hole diameters after etching. It can also measure CD imbalances after SAQP processes. In addition, it enables precisely obtaining intra-shot CD distribution based on the distribution over the entire surface of a wafer. We evaluated this technology using actual device wafers. CD imbalances of SAQP on DRAM process wafers were measured, within a few minutes across a wafer, at an accuracy of |X|+3σ<0.5 nm. CD changes at the outermost area of the wafer were captured by CD measurement of 27 nm hole patterns on a DRAM process wafer. Random CD defects were captured by CD measurement of 38 nm hole patterns on a DRAM process wafer. These defects affect device yield but were not detectable by using conventional inspection tools.
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