Semiconductor metal oxide (SMO) sensors have been utilized as oxygen sensors in industry and research for decades. Oxygen molecules adsorb to the SMO surface which leads to a measurable increase of resistivity [1]. Those sensors are valued for their high accuracy, but they operate at high temperatures [2]. Therefore, heating circuits inside the sensors are required, increasing size and power consumption of the sensors. This paper investigates the applicability of zinc oxide nanoparticle (ZnO) structures as low-cost oxygen detectors for measurements at room temperature. The main advantage of ZnO nanoparticle-based electronics is their low production cost since the nanoparticles can be deposited by cheap process techniques like spray-coating, spin-coating, inkjet-printing or the doctor blade process. Furthermore, they provide a high surface area to volume ratio which leads to higher sensitivity to oxygen. The most critical disadvantage is the high inhomogeneity of particle size and shape which causes nanoporous ZnO layers with low conductivity and nonuniform electrical characteristics. Therefore, gate structures were integrated into the sensors, so that the ZnO nanoparticle conductivity can be adjusted by applying a gate voltage. ZnO nanoparticle transistors with different electrode geometries and channel length were manufactured and analyzed. In different oxygen concentrations ZnO layer resistance, dependent on the applied gate voltage, was measured. Based on the results, a new layout for low-cost sensors without heating structures was developed. Since this work is part of a project, in which a low-cost water quality sensor is developed, the sensors are designed for oxygen concentration measurements in liquids as well.
Inkjet-printed capacitive circuits on different substrates will be investigated. This work will contribute towards rapidly prototyping electronic systems for smart ubiquitous biosensors. These biosensors require sensitive and robust signal readout with low power consumption and wireless connectivity while also being inexpensive. Capacitors were printed on different substrates, including glass and overhead projector film, to characterize an inkjet-printed dielectric. A Fujifilm Dimatix DMP2831 was used to print different functional inks, including Harima silver nanoparticle ink and InkEpo-XP ink. The silver nanoparticle ink was used to print the conductive features of the capacitors while the InkEpo-XP was used as the dielectric material. Different test patterns were printed with silver ink on the dielectric material; these patterns were used to establish a printing protocol for successful printing of silver on the dielectric material. Different test patterns were also printed with dielectric ink on silver to create a printing protocol for successfully printing dielectric on silver. Metal-insulator-metal capacitors were successfully inkjet printed on glass and overhead projector film with silver and dielectric inks. The metal-insulator-metal capacitors were used to characterize the dielectric material at different frequencies. The circuit modelling of the capacitors is discussed, and validated against experimental results. A design procedure is presented for reliably printing capacitive networks with feature dimensions between 1 mm and 2 mm on glass and overhead projector film.
Thin-film transistors (TFTs) are the pivotal elements driving electrical current in innovative systems. These applications emerge adding new functionalities to every-day products; therefore, new challenges are faced. Electric components in flexible displays, RFID tags, or electronics skin for health monitoring are subjected to a high degree of mechanical deformation. Nonetheless, the systems have to operate properly despite external influences. In this study, a brief review of the mechanical deformation on the electrical characteristics of nanoparticle-based TFTs is presented Conjointly, a case-of-study considering low-cost ZnO nanoparticle-based TFTs on PET substrate is analyzed. The TFTs were integrated on a freestanding substrate replicating a more realistic scenario for a later large-scale production. Fabrication steps with a maximum temperature of 120°C were employed availing the integration process to a wider range of substrates. As gate dielectric, a spin-on highk nanocomposite was selected in order to favor the mechanical stability of the layer as well as its permittivity. Moreover, the integration routine was adapted in order to reduce parasitic overlapping capacitances in the transistors. The TFTs were electrically characterized either in a flat state or under mechanical deformation, employing different bending directions as well as deformations parallel or perpendicular to the transistor channel.
This study focuses on the integration of copper oxide nanoparticles forming inorganic p-channel thin-film transistors (TFTs). The used CuO nanoparticles have a diameter of 25-55 nm and are dispersed in a water-based solution providing the opportunity of low-cost and large-scale integration processes. First investigations were realized using an inverted coplanar TFT architecture due to the low chemical and physical stresses the semiconductor has to withstand. Therefore, a gate electrode consisting of 50 nm aluminum followed by 7 nm titanium was integrated on a Si/SiO2 substrate. As gate dielectric a high-k organic-inorganic nanocomposite was deposited by spin-coating resulting in a layer thickness of 150- 180 nm. For the drain and source electrodes gold and nickel were examined. For both metallizations the influence of an electrode treatment with a self-assembling monolayer (2,3,4,5,6 Pentafluorothiophenol, PFBT) was investigated. The gate metallization as well as the drain/source electrodes were evaporated via e-beam and structured by photolithography followed by wet-etching processes and lift-off technique, respectively. In the last step, the CuO nanoparticle layer was applied by doctor blade process followed by evaporating the solvent in a convection oven under ambient conditions. The maximum temperature during the integration process was 115°C so that a compatibility to glass and foil substrates is given. The influence of the drain/source material on the electrical characteristics was explored as well as the impact of the electrode treatment. Besides single TFTs inorganic inverter circuits in complementary technique were analyzed.
In this study, we present the development of a doctor blade system for the deposition of thin semiconducting films by solution casting. The developed system allows a low-cost production of thin-film transistors (TFT) on large-area substrates. The deposition parameters like the velocity of the doctor blade and the temperature of the substrate affect the layer thickness and process quality directly and should be analyzed to improve the deposition quality. The developed system is operated by a microcontroller, which is responsible for adjusting the motor velocity and controlling the substrate temperature. The control system allows setting the velocity between 1 and 500 μm/s and the substrate temperature from 20 to 100°C. The implemented LCD display with control elements provides the user interface and allows setting up and controlling the process parameters. The high quality step motor drives the linear actuator with the attached substrate and realizes the relative movement of the doctor blade over the substrate. The micro-step control algorithm provides the high resolution and smooth movement of the substrate. The heating system is realized by a self-adhesive heating film and sensor element, mounted on the substrate. Additionally, an ultrasonic excitation of the doctor blade realized by an attached ultrasonic transducer can be used to improve the layer quality.
The digitalization is one of the main driving force for technologic developments in the area of low-cost electronics. Sensors and RFID tags should be integrated possibly at low-cost to easily upgrade everyday objects with new functionalities. Key elements of such upgrading objects are often thin-film transistors (TFTs). In this article we analysed two different commercially available, high-k nanocomposites ino®flex Z3 and ino®flex T3 regarding their frequencydependent dielectric constant and surface properties. TFTs using either ino®flex Z3 or ino®flex T3 as gate dielectric were fabricated using common photolithographic integration methods and subsequently electrically analysed. For further device optimization a self-aligning integration technique was used utilising the nanocomposite ino®flex T3 as gate dielectric. For all integrated TFTs, dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) was used as active semiconductor.
The Internet of Things (IoT) is a main driving force for research efforts in the area of low-cost electronics. Low-cost solutions for the upgrade of already existing everyday objects by sensors or RFID tags are needed. Key elements of such upgrading technologies are often thin-film transistors (TFTs). In this article we analysed the structurability of the commercially available, high-k dielectric ino® flex T3 by means of common used optical photolithographic techniques and wet-etching processes and its influence on the TFT performance. Furthermore, the impact of an alkanethiol treatment of the drain and source contacts on the charge carrier injection from the metal into the semiconducting layer was investigated. As active semiconductor a dithienothiophene (DTT) derivate was used.
Key issues for flexible electronics are low temperature processing, cost-efficient semiconducting and dielectric materials, and sufficient performance of the integrated TFT devices. To achieve high performance flexible circuits, contact resistances of today’s transistors must be reduced. Additionally, the parasitic overlap capacitances between the transistor’s electrodes need to be minimized. The inverted staggered transistor setup with self-aligned gate fulfills these requests. Nevertheless, the integrated devices suffer on poor AC characteristics due to limited performance of the common gate dielectric layers. The gate voltage has no direct access to the semiconductor surface, either due to rechargeable surface states and polarization effects or because of low-k values. Consequently, new flexible high-k dielectrics must be implemented in TFT device integration.
Nowadays, thin-film transistors (TFTs) are being actively researched not only by the scientific community but also by the industry. They are the crucial elements for the driving currents in flexible displays, radio frequency identification tags and wearable electronic skins. In this study, we present a low-cost integration process of ZnO nanoparticle TFTs on flexible substrates with a maximum process temperature limited to 115 °C. As gate dielectric a high-k resin filled with TiO2 nanoparticle was used. This nanocomposite combines the mechanical flexibility of organic compounds with the high dielectric permittivity of inorganic materials. For the stabilization of the nanoparticulated ZnO film, a high humidity treatment was performed subsequent to an ultra-violet irradiation step in order to prevent the adsorption of oxygen molecules by the nanoparticles. The transistor integration process was performed on a freestanding polyethylene terephthalate (PET) substrate. This technique enables a more realistic scenario for a later large-scale production and avails adequate photolithographic resolution and accurate alignment between different mask levels. Additionally, in order to improve the electrical properties of the nanoparticulated semiconducting film, the nanoparticles were deposited using either spin-coating or spray-coating techniques; furthermore, different surface pretreatments were executed.
Thermoelectric generators (TEGs) can be used as robust and maintenance-free power supplies. The power
density of currently available TEGs is about 1 W/cm² and sufficient for many low power
sensor/microelectromechanical systems. By changing the sintering atmosphere and using a special set-up a
standard industry process used for insulating or metallic materials was transferred to thermoelectric FeSi2-,
Mg2Si- and SiGe-material. Thereby, separated compact- and sintering steps allows a mass producible process
in contrast to the almost exclusively used SPS- and FAST-processes. All three materials have been further
processed to functional TEG-modules by sawing, bonding and electrically contacting with TiSi2. Thereby, the
mechanical bond as well as the electrical contacts are thermally stable up to 800 °C. The general functionality
and the characteristics of the final TEG-modules were confirmed by analysis in a measurement setup that
simulates an application in a realistic environment.
Key issues for flexible complementary electronics are low temperature processing, sufficient performance of the
integrated p- and n-type FET devices, and cheap semiconducting and dielectric materials. Organic semiconductors
commonly depict p-type behavior, whereas metal oxide semiconductors show n-type characteristics. This paper presents
a new approach for common integration of organic and ZnO transistors on transparent substrates for complementary
transistor electronics. The gate dielectric consists of a special high-k resin, the metallization utilizes Au and Al films. The
thermal budget for processing of the devices is limited to 120°C to enable foil substrates.
High efficient dye sensitized solar cells typically apply expensive materials. To reduce the costs natural dyes, carbon
nanotubes and an additional contact layer were introduced. UV-irradiation substitutes typical sintering processes for the
TiO2 nanoparticle film. Replacing the ITO coated glass electrodes by a metal grid structure reduces the integration costs
further more. Best results were achieved using a grid structure with openings in the dimension of the diffusion length of
the charge carriers.
Potentiometry with a Kelvin probe atomic force microscope is used to investigate the contact resistances of pentacene OFETs, so that the injection of the charges at the source contact and their extraction at the drain contact can be distinguished from the influence of trap
states on the charge transport through the accumulation channel. The
samples consist of Au bottom contacts on a SiO2 gate dielectric with a channel length of L=10- 15 μm and a channel
width of W=100 μm. The gate oxide is first treated by an
oxygen plasma before depositing about 30 nm of pentacene under high
vacuum conditions. The output characteristics are measured as a
function of temperature in an evacuated cryostat, revealing
temperature-activated hole transport. The potentiometry measurements
are performed ex situ under atmospheric conditions after storing
the samples in air for several weeks. At room temperature, the
pentacene OFETs are dominated by the resistance at the injection
contact, so that the mobility in the channel region as deduced from
potentiometry is about one order of magnitude higher than the value
obtained from the output characteristics. The measurements are
interpreted with microscopic model calculations for the
temperature-activated currents.
The fabrication of piezo-resistive pressure sensors for high temperature applications by the selective removal of CVD-diamond is limited due to the jutting physical properties of this material, which result in insufficient etching rates. A novel technique with distinctly increased etching rates due to a modified sample arrangement inside of a commercially available reactive ion etching (RIE) reactor overcomes this limitation by a restricted plasma volume. Rates up to 334 nm/min imply an increase of more than one order of magnitude in comparison with additional measurements utilizing a standard etching technique. Furthermore, the electrical response of a fabricated sensor on pressure is demonstrated.
Organic thin film transistors on silicon substrate are fabricated by standard lithography techniques to get transistors with micrometer scale gate length. The semiconducting layer consists of the evaporated organic molecule Pentacene. Transistor parameters taken from transistors with channel lengths of 10 μm - 1 μm confirm the validity of the models for silicon MOS transistors. For further reduction in channel length the imprint technique is proposed to integrate sub micron distances between the drain and source metallization of the transistor.
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