Proceedings Article | 1 May 2023
KEYWORDS: Nanoimprint lithography, Semiconducting wafers, Overlay metrology, Particles, Optical lithography, Logic, Distortion, Semiconductors, Optical components, Molybdenum
Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. In this paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. We specifically focus on performance improvements related to overlay, edge placement error and defectivity. For overlay, we present results on stability and also discuss new methods to further address high order distortion. For edge placement error (EPE), we discuss progress made towards addressing EPE budgets for memory devices. For defectivity, we review random defect generation, particle adders and mask inspection methods. NIL usability cases are also examined. In addition, we also discuss Canon’s recent involvement in the New Energy and Industrial Technology Development Organization (NEDO) project and its goals related to logic devices. As a final topic, we describe Canon’s interests in fabrication beyond traditional advanced semiconductor devices.
