Bolometers are used extensively in astrophysics for imaging and spectroscopy at wavelengths between several millimeters and 10 microns. They are particularly useful for applications requiring high sensitivity; current and planned bolometer systems are nearing the sensitivity limit imposed by background photon noise, even in the low-background conditions achieved in observatories on satellites, aircraft, and balloons. Reaching this limit will require new types of bolometers as well as improved preamplifiers to read them out. We describe two types of bolometers optimized for low-background operation and focus on the design and testing of their preamplifier circuits.

Gallium arsenide junction field-effect transistors (GaAs JFETs) are promising for deep cryogenic (< 10 K) readout electronics applications. This paper presents the structure and fabrication of GaAs (JFETs) and their performance at 4 K. It is shown that these JFETs operate normally at 4 K, with no anomalous behavior such as kinks or hysteresis. The noise voltage follows a 1/(root)f dependence and is approximately 1 (mu) v/(root)Hz at 1 Hz for a ring JFET that is 1250 micrometers in circumference and 20 micrometers long. The gate leakage current reaches 1 pA at a gate voltage of -6 V, and increases exponentially at approximately 1 decade per volt. The noise is within the limits of the requirements for typical VLWIR readout applications; the extrapolated gate leakage current at typical operating biases is higher than the required limit by two orders of magnitude. Planned improvements to reduce the leakage current are discussed.

The far-infrared is a key wavelength regime for astronomical observations. Until recently, however, development of useful large format arrays at these wavelengths has been hampered by the lack of suitable readouts that operate well at the very low temperatures required by these detectors. We report on the initial characterization of CRC-696 readouts fabricated at the Hughes Technology Center (Carlsbad CA) specifically built to operate at 4 K and lower. These devices have been optimized to work with extrinsic germanium photoconductors. At these low temperatures, the fully multiplexed 32-channel readouts has a read noise below 30 electrons at a power dissipation of 1 (mu) W per channel. We also report on the testing of the first complete focal plane module fabricated with these devices. This module is operating at a level of performance (dark current, noise, stability, and power dissipation) that make arrays built with this technology suitable candidates for the next generation of space infrared observatories.

We have developed a new architecture for a superconducting high-resolution analog-to-digital converter (ADC) which is highly beneficial for IR array readout applications due to its high sensitivity, wide dynamic range and sub-mW power consumption. This ADC is based on the principles of magnetic flux quantization, direct differential coding and decimation filtering. The digital part of the ADC employs elements of the Rapid Single Flux Quantum logic family which are capable of clock frequencies in excess of 100 GHz. We discuss the limits of ADC performance and present an analysis of the power consumption in these ADCs. We also report experimental verification of several key components of this architecture in Niobium technology (operating at 4.2 K), particularly the implementation of a synchronizer unit (necessary for the generation of the differential digital code) as well as a dual-counter synchronous ADC.

We present the first measurements of silicon-generated (SiGe) heterojunction bipolar transistors (HBT) in the liquid-helium temperature regime. We have measured the dc characteristics of SiGe HBTs from two different profile designs over the temperature range of 300 K - 4 K. The first SiGe HBT design was optimized for high-speed digital applications at room temperature (`i-p-i' SiGe HBT), and the second SiGe HBT design was specifically optimized for cryogenic operation (`emitter-cap' SiGe HBT). A silicon bipolar junction transfer (Si BJT) which has a doping profile similar to the i-p-i SiGe HBT is used as a control. The devices continue to exhibit transistor action down to the liquid-helium temperature regime, even in the presence of strong carrier freeze-out in the neutral base and collector regimes. In contrast to the Si BJT, the peak current gain of the optimized emitter-cap SiGe HBT rises monotonically from 100 to 300 K to nearly 2000 at 16 K, although parasitic base current leakage limits the useful operating range to collector currents above about 1.0 (mu) A. At very low-injection levels (less than 1.0 nA) below 77 K, we identify a non- diffusive transport mechanism in the collector current of both SiGe HBTs and the Si BJT which is unaccounted for in conventional device theory. Initial calculations suggest that this phenomenon has a bias and temperature dependence characteristic of a carrier tunneling process.

We report successful coupling of electrical signals from low temperature (4.2 K) superconducting circuitry to room temperature electronics using laser diodes coupled to optical fibers. The techniques used rely on laser diodes operating at low temperatures, and on high gain amplifiers placed outside the low temperature environment. A new superconducting driver circuit is used to step-up the low output of these circuits to a seven millivolt level, sufficient to modulate the laser diodes. By properly choosing the laser source, the power dissipated within the cryogenic environment can be maintained below 400 (mu) W, with further improvements easily reached.

Rockwell International has developed 128 X 128 element multiplexers and very-long- wavelength infrared (VLWIR), Si:As blocked impurity band (BIB) hybrid focal plane arrays (HFPAs) for both low and high flux applications. The multiplexers are fabricated with an n- well CMOS process with 2 micrometers design rules optimized for the <EQ 14 K operating temperature of Si:As BIB detectors. For low flux applications, the unit cell integration capacitance has been reduced to values as small as 0.133 pF and measures to reduce multiplexer photon emission have been implemented. For the high flux regime, the unit cell charge capacity has been maximized with a direct injection input (for large integrated voltage swing) and by using large in-cell capacitance. Devices with a large number of high speed output lines (16) for high frame rate operation have been developed. High quality (near 100% pixel operability with very small (< 3%) nonuniformity) HFPAs have been repeatedly demonstrated with both types of arrays. An improved cryogenic multiplexer process, with 1.2 micrometers design rules, is being used to design and lay out a 256 X 256 element multiplexer for a BIB HFPA. This array, expected in late 1994, will be optimized for high flux applications and will provide improved capability for ground-based, VLWIR imaging instruments for astronomy and other applications.

Results are presented of a process-development effort to achieve a 1-Mrad silicon (Si) radiation-hardening capability at temperatures down to 40 K, using Texas Instruments high volume, 1-micrometer commercial process. The one-micrometer process was characterized at 77 K and 40 K: radiation effects on the baseline SiO₂ gate dielectric and N-channel field effect transistor edges were observed, as were freeze-out and hot-carrier effects of the lightly doped drain implants. These freeze-out phenomena were confirmed, using SUPREM, MINIMOS, and MEDICI. The simulated data compared favorably with measured results. Simulations were run, using various implant doses and profiles to eliminate the freeze-out and hot-carrier effects in the new process. Devices having these simulated profiles were processed, and the results are presented.

Cryogenic signal processing and A/D conversion for the IR imaging and high energy physics experiment applications place severe demands on the silicon process involved, particularly in ionizing radiation environments. This paper describes a process specifically optimized for operation in the 40 K - 77 K temperature range in a total dose environment. Trade-offs of hardness, supply voltage and hot electron vulnerability are discussed and preliminary device- level results are shown.

Hole trapping phenomena by substrate hot carrier (SHC) stressing and ionizing radiation are compared. Similar effects on device characteristics such as transconductance change, threshold voltage (V_t) shift etc due to SHC stressing and ionizing radiation are observed. Less radiation induced V_t shift is observed for SHC stressed device than that due to virgin device. Though the hole traps due to SHC stressing and ionizing irradiation anneal with applied field, their annealing behavior is markedly different. It is due to the fact that the hole trap distribution is different for SHC stressing condition than that due to ionizing irradiation.

The wide availability of 2D arrays of IR detectors has resulted in a profound change in the capabilities and perspectives for IR astronomy. As a consequence, astronomical users of these arrays, in both ground-based and space applications, have placed new and, in some cases, difficult requirements on new IR array detector and multiplexer technology. In this paper the most important of these requirements are listed and discussed.

Santa Barbara Research Center, Hughes, and Hughes Technology Center have designed and built second generation readout circuits since the early 70's. This paper will discuss the evolution, problem areas, and system design drivers that drove the development of these circuits. The discussion will range from the earliest monolithic implementation of the readouts to the newer hybrid approaches which incorporate a high level of integration. Areas addressed will be the transition from NMOS or PMOS to CMOS, development of design rule's technology, yields, costs, and performance. All these topics will show how these developments affected readouts and second generation infrared sensors. We shall also speculate on the future developments in ROIC technology.

A response model that describes an optimal imager with a photodiode-direct injection readout focal plane is developed and a time-domain computer simulation based on this model is executed for different background radiance levels. For small signals, the model explains in detail why small photodiode capacitance, and high background photoflux levels are necessary to maintain good optical resolution. However, unlike the small-signal model, the large-signal model is valid throughout the range of parameters and gives the response for large signal-to- noise ratio and low background cases.

In order to improve the uniformity and yield of the focal plane arrays being used in Cincinnati Electronics infrared camera systems, the multiplexer is being upgraded to include a feedback enhancing buffer amplifier in its unit cell. A test die containing variations of a buffered direct injection circuit, along with some of its constituent parts, has been fabricated and tested. The test results have been compared with predicted performance from SPICE modeling of the circuit, and generally good agreement has been obtained. The results indicate with only a modestly sized buffer amplifier, sufficient performance improvement can be obtained to significantly improve the device yield for the infrared camera focal plane array.

The use of a multiple dielectric gate insulator, and the addition of a gate insulator extension and guard-bars to the NMOS transistors, has resulted in a significant increase in total-dose ionizing radiation resistance for CMOS IR readout multiplexer circuits operating at cryogenic temperatures. This paper describes the implementation of these modifications, and also some observed anomalous transistor offset voltages that were apparently due to charges trapped in the multiple dielectric gate insulator during the circuit fabrication process.

The multiplexer being used in the focal plane array for the Cassini Visible and Infrared Mapping Spectrometer has received extensive characterization. The multiplexer is a capacitive transimpedance amplifier line array having very low noise, and fabricated using a radiation hardened CMOS process. Details of the amplifier characteristics as well as results from multiplexer and FPA testing have been obtained. The results show that the multiplexer will be able to meet the focal plane array mission objectives.

A design is presented for 512-element CTIA multiplexer developed for readout of an array of 1024-element InGaAs detectors for operation with a bias voltage in the range of +/- 10 mV. This multiplexer can be operated with a left-to-right or right-to-left scan, a non- destructive sequential readout with line-by-line selectable detector reset, and with or without input-MOSFET-threshold uniformity correction. The optical integration time in the range from 20 ms to 10 min is selectable in multiples of 20 to 40 ms line times. The multiplexer cell architecture includes a differential CTIA with open-loop gain of about 5000, a CDS circuit, and two unity-grain buffer amplifiers.

In a project instigated by a proposed upgrade to the Airborne Visible and Infrared Imaging Spectrometer (AVIRIS) focal plane array assemblies, a set of multiplexers are being designed and fabricated. These circuits span the gamut of typical infrared multiplexer design, ranging from buffered direct injection, to transimpedance amplifiers, to source follower detector integrators. All are designed to be compatible with the existing AVIRIS detector assembly, and to be as electronically and mechanically inter-compatible as possible.

The operation of an optical communication link employing a Mach-Zehnder Interferometer fabricated from has been demonstrated in a cryogenic environment. Using simulated analog signals from a cryogenic IR focal plane array, the optical transfer of low level electrical signals between the areas of temperature extremes has been demonstrated. The bandwidth, signal to noise, and dynamic range for the link was measured and a relationship for the transfer gain developed. Packaging considerations for long term reliable operation at cryogenic temperatures is addressed.

This paper presents approaches for on-focal-plane analog-to-digital conversion (ADC). Common approaches and architectures for ADC and their utility for on-focal-plane integration are discussed. Candidate approaches are analyzed with respect to required amplifier gain, bandwidth, capacitance matching, noise and offsets as a function of ADC resolution. A column-parallel ADC architecture appears to be an effective compromise of chip area, power, circuit speed and ADC resolution. The discussion is valid for both infrared focal-plane arrays and visible image sensors.

A number or novel building blocks for constructing early vision neural networks in silicon is presented. It is also shown, that a coding of information with a rate of spikes is a promising strategy in developing both local and global architecture of these networks.

Visible and infrared focal planes are becoming ever larger and more complicated, but the real estate for unit cell electronics is diminishing. Applications such as High Definition Television require very large format focal plane arrays and complex post image processing prior to data transmission. The authors describe in this paper a technique of combining an active pixel CMOS sensor, or a CCD image capture device with analog to digital conversion and data compression circuitry on the focal plane in a unique Z-technology architecture. This architecture incorporates a stack of signal processing integrated circuits physically connected below the image capture device which provides up to 10 times the unit cell electronics real estate for the data conditioning. This paper focuses on the interconnect techniques between the image capture device and the post processing electronics.

Charge-coupled devices (CCDs) are often utilized as image readout devices in infrared focal plane arrays. In hybrid structures, the signal charge generated in the IR-sensitive detector elements is typically injected into the silicon CCD potential wells using `bump' technology. The floating diffusion output structure, which is regularly used in today's CCDs, also when used in the visible spectrum, generates an output video signal in which each pixel is represented by the voltage difference between the `reference level' and the `signal level'.

Drain voltages of a test structure of dual gate MOS-JFET CCD (TIJ J032) were measured by an advanced laser scanner. The potential variation of the test structure at various source and gate voltages were measured by monitoring drain voltages with respect to the scanning laser position. In this report, a fine continuous, constant energy He-Ne laser beam of the Multipurpose Microelectronic Advanced Laser Scanner is utilized for the characterization of local variation of the sensor performance within the test structure.

The increased interest in cryogenic semiconductors and new cryogenic processes that operate at 40 K has prompted the development of a tester to analyze low temperature reliability physics. This tester is particularly suited to study hot electron (hot e-) effects at LN₂ temperatures but also capable of performing time dependent dielectric breakdown studies. The objective of this work was to study hot electron effects at low temperatures and its activation energy over a large temperature range for conventional thermal oxides in the 150 to 200 angstroms range. It has been shown over the last several years that low temperature operation can significantly enhance the hot electron degradation of a transistor.