Surface Charge Analysis (SCA) has been successfully used to monitor oxidation furnaces in semiconductor production fabs. Recently, surface lifetime and higher levels of induced charge (Hi-Q) options have become available to SCA instrumentation, opening an avenue for detecting heavy metals and a wider range of dielectric charges. In this paper, data on the evaluation of these new options is reviewed. It is found that lifetime measurements are affected by both oxygen content in the substrate as well as metal contaminants on the wafer surface. 30 ppms oxygen content in the wafer degrades lifetime more than 10¹¹ - 10¹²/cm² metal contaminants on the wafer surface. The Hi-Q module in turn permits the evaluation of even unannealed LPCVD and PECVD dielectric films, previously out of instrumental range due to their high level of charge. Within the 2.6E12/cm² charge limit, SCA shows that oxide charge (Qox) is inversely proportional to deposition temperature of both TEOS and nitride, and is proportional to NH₃/DCS ratio for nitride. SCA also shows that certain anneal ambients for PETEOS can cause field Vt changes by annihilating or generating charges in the dielectric films. In short, both the lifetime and Hi-Q enhancements of SCA are shown to offer added capabilities for evaluating metallic contamination if oxygen-free substrates are used, and for deposited dielectrics within the fab as long as the charge is below 2.6E12/cm².

Oxide process monitoring for process deviations and contamination is essential for achieving high performance and yield in advanced integrated circuits. Moreover, monitoring techniques must be able to frequently measure actual production-critical films to minimize the cost of monitoring and to minimize the product at risk. A methodology and experimental results for qualifying a surface charge analyzer (SCA) for in-line monitoring of ultrathin oxides (less than 30 angstroms) are presented. The SCA provides rapid measurements of total oxide charge, density of interface traps, minority carrier recombination lifetime and doping concentration with sensitivities that are independent of oxide thickness. Process deviations in anneal, pre-clean, oxidation recipe and wafer substrate, were intentionally introduced on sample wafers. All wafers with intentional process deviations were detected by the SCA. Process tolerance and SCA precision were also estimated. The SCA meets the requirements for an in-line process monitor by performing rapid, repeatable and cost effective measurements on ultrathin oxide production recipes.

Metallic contamination was monitored with Surface Photovoltage (SPV) technique in integrated circuit manufacturing facilities. Conventionally, Czochralski silicon bulk materials were used as monitor wafers. However, it has been observed that the diffusion length and the `Iron' concentration measured with SPV were inconsistent from run to run in one facility. The inconsistency is believed to be due to oxygen precipitate in silicon materials during the thermal cycle. By using low oxygen concentration or Float Zone wafers, metallic contaminants can be monitored more accurately and consistently.

In-line monitoring of silicon dioxide film properties using non-contact or non-destructive techniques is quickly gaining industry acceptance as an alternative to conventional electrical and analytical methods. Mobile ion measurement in oxides using the corona temperature stress (CTS) technique was first discussed in the early 1970's. However, CTS measurements have only recently become available in a new generation of measurement tools. The CTS method may be applied immediately following film growth and does not depend on the fabrication of electrical test structures. This paper addresses the sensitivity and repeatability of the CTS approach with results of measurements performed, using a Semiconductor Diagnostics, Inc. mobile charge/plasma damage monitor system, on a variety of intentionally contaminated oxides. All oxide growth and characterization was performed on 200 mm diameter silicon wafers in a state- of-the-art manufacturing facility. Both chlorinated and non- chlorinated oxides were tested in addition to the effects of growth conditions that resulted in high charge density at the silicon-silicon dioxide interface. Water solutions containing sodium in the range from 10 to 1 ppba were used to introduce the contamination to the oxides. Photovoltage measurements, conventional C-V (capacitance-voltage) testing, and SIMS analysis were also performed to assess the quality of the oxides and to provide correlation to the corona mobile charge measurements.

Existing methods for measuring the resistivity of epitaxial wafers suffer from the following problems: wafer damage, slow turn-around time, poor repeatability and sensitivity to surface conditions. A new technique for in-line non-contact measurement of the resistivity profile in semiconductor wafers, free of the above problems, is described and experimental data presented. In this method, modulated light is directed at the specimen, while the dc surface potential of the specimen is varied between that corresponding to accumulation and that corresponding to deep depletion. The light intensity is sufficiently low and the dc surface potential is varied sufficiently fast to ensure that the surface concentration of optically generated minority carriers is negligible compared to the surface density of the depletion area space charge. The depletion width of the space charge region is calculated from the ac surface photosignal, generated by the modulated light beam, and its dependence on the induced space charge is used to derive various parameters of the specimen including the resistivity, doping concentration profile and epitaxial layer thickness. The high rate of change of the dc surface potential minimizes the effects of surface states recharging, which allows use of this method for characterization of non-passivated wafers. The non-contact nature of the method makes it applicable for monitoring of production wafers.

Improvement of recombination properties is observed in EFG microcrystalline Si wafers subjected to consecutive solar cell processing steps. A dramatic increase of room- temperature band-to-band photoluminescence (PL) intensity (hv_max equals 1.1 eV) by a factor of two orders of magnitude occurs in the solar cell, to demonstrate a significant reduction in non-radiative recombination during the upgrading steps that benefit solar cell efficiency. Using spatially resolved PL mapping over 100 cm2 wafers, we study PL behavior in solar cell fabrication. We compared point-by-point PL mapping with distribution of minority carrier diffusion length in the same poly-Si wafer. A correlation between PL intensity and the diffusion length is documented using a statistically valid data-base. It is suggested that room-temperature PL mapping can be used for on-line monitoring of poly-Si solar cell quality.

Chemical mechanical polishing (CMP) generates unique difficulties for defect metrology using wafer scanners. Polishing residue, scratches, pits, normal contaminant particles and the pattern covered by the planarized material provide scattering signatures that differ from normal patterned or unpatterned wafers. This relatively young application area for wafer inspection instruments needs a rapid infusion of experience and knowledge infrastructure in order to bring it along to the level of more conventional applications. To that end, a series of relevant experiments have been completed on three types of tungsten (W) CMP test wafers including (1) partially-polished blanket W, (2) fully-polished blanket wafers (polished to oxide), and (3) fully-polished patterned W wafers. Various contamination particles and defects on these wafers were characterized and identified by means of optical microscopy, surface scanning inspection, scanning electron microscopy, energy-dispersive x-ray spectrometry, and atomic force microscopy. A number of defect types including: particles of polished material, substrate, abrasive, oxidizer, and chemical products of polished material and oxidizer; scratches; and pits were expected based on an analysis of the CMP process, and were thereafter confirmed by experiment. Surface roughness was measured on the two types of blanket wafers. W line roughness and dishing depth were measured as a function of line width and pattern density on the patterned W wafers. For light scattering experiments, 0.482 micrometers polystyrene latex spheres were deposited on a patterned W CMP test wafer. Differential light scattering cross sections of particles located in the 0.5 micrometers line/1.0 micrometers pitch region at various locations relative to the W lines were then measured at 488 nm wavelength using the Arizona State University scatterometer.

Electrical defect density is simply a model or measurement of the number of electrical defects per unit area, which is a summation of yield loss from several sources, broadly classified into random and systematic failures. Random failure is typically from in-line defects (from equipment, process); systematic failure is from process marginality, parametric failure or design sensitivity. Assuming that after some amount of time systematic issues are mostly worked out, yield is then essentially defect limited, as is the case for most mature fabs/mature products running today. In this scenario, electrical defects density should hold to a predictable pattern dependent on minimum line width, process complexity and layout density (critical area). Understanding these relationships will greatly increase our ability to predict (defect limited) yield for new products at new technologies. The calculation of a critical area parameter, A_c, will be used in place of the area in electrical defect density calculations to obtain a critical area compensated DD that should be independent of device/design structure related effects. In addition, use of the critical area probability of fail curves will be used to estimate yield loss in-line and drive future defect improvements.

The advent of ultra-large and giga-scale-integration (ULSI/GSI) has placed considerable emphasis on the development of new gate oxides and interlevel dielectrics capable of meeting strict performance and reliability requirements. The costs and demands associated with ULSI fabrication have in turn fueled the need for cost-effective, rapid and accurate in-line characterization techniques for evaluating dielectric quality. The use of non-contact surface photovoltage characterization techniques provides cost-effective rapid feedback on dielectric quality, reducing costs through the reutilization of control wafers and the elimination of processing time. This technology has been applied to characterize most of the relevant C-V parameters, including flatband voltage (V_fb), density of interface traps (D_it), mobile charge density (Q_m), oxide thickness (T_ox), oxide resistivity (p_ox) and total charge (Q_tot) for gate and interlevel (ILO) oxides. A novel method of measuring tunneling voltage by this technique on various gate oxides is discussed. For ILO, PECVD and high density plasma dielectrics, surface voltage maps are also presented. Measurements of near-surface silicon quality are described, including minority carrier generation lifetime, and examples of their application in diagnosing manufacturing problems.

A new measurement technique for process monitoring that consists of observing current or charge transients after each voltage step during cyclic voltage sweeps is presented. This technique provides a quick turn-around alternative to monitoring with full-flow CMOS devices since it uses simple ultrathin oxide MOS structures. Analysis of the resulting cyclic I-V and Q-V data provides important physical information about the status of the ultrathin oxide, the interface and the near surface Si region.

As the cost per finished wafer increases, in-line characterization becomes an effective way to identify and control critical process parameters prior to end-of-line. In-line characterization enables testing of important process specifications during fabrication. By using in-line characterization, process problems can be immediately discovered. Alternatively, waiting for results from parametric probe can be a costly choice. This work focuses on the application of in-line electrical measurement of critical oxide thicknesses for process control. Specifically, in-line characterization is being applied to test structures in an effort to electrically characterize tunnel oxide thickness on Non-Volatile Memory parts. Using a Keithley Semiconductor Metrology System we have been able to obtain this electrical information without the need to scrap material following the measurement. We will summarize the necessary steps for implementation of such an electrical test and we will present a methodology to control film thickness using the results of electrical measurements.

As process complexity and number of plasma processing steps increase, process-induced charging damage becomes an emerging issue in continuously scaling device manufacturing. It is important, therefore, to be able to pinpoint most of potential sources of plasma charging-induced damage. The most commonly used approach involves processing and testing of several modules of antenna-type transistors, with charge sensitive antennas defined and exposed to plasma at various stages of processing. Subsequent analysis of damage allows determination of the processing level at which most of damage occurred. This work presents an alternative and complementary approach to assess potential sources of charging damage. This approach is based on in-line testing of gate oxide integrity of a MOS transistor structure with a charge collecting antenna. Gate oxide integrity tests performed after poly-silicon salicidation and after metal-1 level are used to separate the effect of poly etch and inter-layer dielectric deposition. It is shown that by the in-line testing of silicided poly antennas the effect of charging damage due to plasma-enhanced chemical vapor deposition (PECVD) of oxide can be unambiguously determined. The fingerprint of PECVD-induced charging is further documented by the surface charge analysis performed on oxidized silicon wafers exposed to PECVD oxide deposition.

In-line testing methods of thin gate oxide integrity are compared based on oxide breakdown characteristics. The results were obtained on test structures with plasma induced oxide degradation due to the different plasma based deposition and etch processes used in the five metal CMOS fabrication. Voltage ramp technique has been identified as the most sensitive and universal technique to investigate breakdown characteristics. In order to find out about the possible correlation between the degradation of oxide bulk and the Si/SiO₂ interface, trap density in MOSFETs was also monitored using transconductance and charge pumping measurements. It was found that while interface degradation was indeed more severe in the structures showing lower breakdown voltages, no quantitative relationship with breakdown voltage could be established. Process-induced defect distribution across the wafers will also be discussed.

Advances in the electronic industry toward large-scale integration of semiconductor devices have placed strict demands on the ability to measure and monitor ultratrace levels of impurities. Even though they have been found to have increasingly detrimental impacts on the performance and yield of semiconductor products, organic and non-metal ionic contaminants have not received the same attention as particles and metallics. Method developments for ultratrace measurements of molecular and ionic contamination are far behind the demands. This paper describes the use of different sampling and analytical techniques to assess and monitor molecular and ionic contaminants in cleanroom ambient air and on wafer surfaces. Thermal desorption gas chromatography mass spectrometry/nitrogen phosphorous detector is used for the identification and quantification of organic contaminants. Ammonium (NH₄⁺) and inorganic anions are analyzed by using capillary electrophoresis with indirect UV detection methods. The identification and quantification of specific organic compounds, which outgas from cleanroom ULPA filters and wafer package boxes and tend to adsorb on silicon wafers, will be demonstrated. Ammonium and anion contamination for different wafer cleaning processes will be compared. The capabilities, applications, and limitations of these techniques will be discussed in further details.

Total reflection X-ray fluorescence (TXRF) is a useful tool for rapid, nondestructive monitoring of implant doses in semiconductor manufacturing. For As-doped (10 keV and 80 keV) Si wafers with an implant dose of 3 X 10¹⁵ at/cm², As fluorescence yield and accumulated As+ dose measured by Secondary Ion Mass Spectroscopy (SIMS) have been compared. This comparison between TXRF and SIMS demonstrates the power of TXRF as a new nondestructive technique for in-line shallow implant dose and profile monitoring.

We developed the post CMP cleaning process using cavitation jet in addition to roll sponge cleaning. In this presentation, we discuss the process damage which had been encountered during the cleaning process development using high pressure water. One was erosion and the other was electrostatic charging damage due to high impinging pressure. The tool parameters of cavitation jet were investigated in order to control the cavitation effect for the wafer cleaning process. These process damage were eliminated by control of cavitation power keeping the occurrence of cavity growth and control of the exposure time to the device by cavitation jet. After that, superior cleaning performance was demonstrated by using the combination of cavitation jet and roll sponge cleaner for wafers after CMP.

The method of calculating the defect probability of silicon damage is demonstrated in this paper. The calculated probability is based on the manufacturing capability of lithography and etching process on dimension and overlay control. An useful equation is derived to calculate the defect probability in silicon damage. This method is helpful on determining suitable process control specifications on dimension and overlay for defect reduction and yield improvement.

Considering the coming 300-mm-dia Si wafer era (beyond 0.25 - 0.18 micrometers design rule in MOS devices), occurrence of slip dislocations along <110> directions due to gravitational stress at supporting jigs is still one of the biggest crucial issues in manufacturing ultra-large-scale- integration circuits. This paper describes how to predict slip dislocation onset under gravitational stress upon heat- treating 300-mm-dia wafers. Gravitational stresses for 300- mm-dia wafers are computed using finite element method (COSMOS/M (SRAC Co.)) and converted to resolved shear stresses in {111} slip planes and <110> slip directions. Individual critical stress curves are independently obtained as a function of microdefect density on the basis of formerly proposed thermoelastic model. By comparing both results, conditions to suppress a collective thermoelastic model. By comparing both results, conditions to suppress a collective motion of dislocation due to both the gravitational stress and thermal stress in heat cycles are obtained and also as predictable in wafers larger than 300 mm in diameter. Concurrently, gravitational-stress- induced-dislocations were found to be running [110] direction on (111) or (--111) plane with length of 4 - 5 cm and analyzed to be 60 degree(s)-type in character, terminating at surface in screw-type.

A common problem in die bonding is the non-stick-on-pad (NSOP) when the bond does not pass the pull test. Contaminants are a possible cause of NSOP, particularly if an undesired thick film is developed on the bond pads. Such films effectively diminish the bondability of the pads resulting in a NSOP problem. In one such case Fourier Transform Infra-Red (FTIR) spectroscopy was used to fingerprint the contaminant formed on the bond pads. The contaminant was an aluminum-oxygen-fluorine compound that was very resistant. FTIR showed Al-F bonds and water of hydration. The distinctive chemical signature was critical in solving the NSOP problem quickly. This was accomplished by growing the resistant film under accelerated conditions, thus recreating the compound in the laboratory. Although the chemical compound was not fully identified, the FTIR signature provided confirmation of the compound for various conditions under which it was formed on bond pads. The source of the fluorine was identified and eliminated.

During the last years, optical scatterometry (OS) has become a competitive technique in micrometrology. Not only is it a very rapid and non-destructive method, but it also meets the accuracy needs imposed by nowaday technology. Relative rms- values of one percent and below have been reported for the multi-parametric characterization of submicron profiles. Although being basically a far field approach, the resolution and accuracy limits of imaging optical methods may be overcome to a certain degree. The goal of this paper is to discuss some new aspects of this technique. Particularly, there are two main topics--the improvement of the 2(theta) -principle for the characterization of sublambda gratings and the extension of the optical scatterometry to the measurement of real scene features instead of periodic ones. As for 2(theta) -scatterometry, first the ability of this method for quantitative measurements is shown with a 0.8 micron pitch grating etched in silicon oxide. Second, the polarization sensitivity is investigated with a 512 nm chromium grating on quartz. While the TE polarization is useful for the coarse characterization of the basic profile in terms of linewidth and height, TM polarized light might be the better choice for sensing sidewall variations and other profile subtleties. And third, a new scatterometer design is presented, which enables a simultaneous 2(theta) - measurement providing for an increased measuring throughput. Here, the application as a resist development monitor is outlined. The second main topic is the extension of the OS to single features in a more common sense, i.e., comprising also small groups of lines or spaces. In a former paper, the authors presented the basic principle and first modeling results. Here, further investigations are discussed aiming at the light scatter dependence on the sidewall angle and the characterization of double lines. The simulations confirm the enhanced sensitivity of TM polarized light to variations in the sidewall steepness. Besides, some nearfield calculations reveal how the light interacts with the scatterer.