Scaling of CMOS technology made possible the key appliances of our information technology society, like the PC, mobile communication, and the internet. Reduction of feature sizes for semiconductor devices continued according to Moore's law for the last 25 years in order to achieve higher integration densities, higher speed, lower power consumption, and lower costs. But now, as we approach the sub 100 nm regime, several roadblocks have been predicted for the next generations down to 35 nm. The latest ITRS roadmap 99 describes in detail the challenges which have to be addressed for the future CMOS technology nodes, regarding lithography, metallization, power dissipation, and circuit design. Also for the MOSFET, performance degradation is a big issue. Because this is not a limitation from basic physical laws, novel architectures for MOSFETs will be needed to improve again the electrical characteristics and thus pave the way to much smaller transistors than expected in the past. 25 nm CMOS seems to be feasible using very thin silicon substrates on insulator. Further improvements down to 10 nm are very likely with two gates for the control of the charge carriers. So, it is very likely that CMOS will not end with today's roadmap at 35 nm or even before, but may continue with non bulk devices and fully depleted channels. Finally, tunnelling from source to drain will set an end to the reduction of channel length, which is estimated to be below 5 nm.

Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure. This additional beam routing flexibility allows significant size reduction and process simplification without sacrificing device performance. This innovative 3-D PIC technology platform can be easily extended to create surface-emitting lasers integrated with power monitoring detectors, micro-lenses, external modulators, amplifiers, and other passive and active components. Such added functionality can produce cost--effective solutions for the highest-end laser transmitters required for datacom and short range telecom networks, as well as fiber channels and other cost and performance sensitive applications. We present results for 1310 nm photonic IC surface-emitting laser transmitters operating at 2.5 Gbps without active thermal electric cooling.

The state of the art of silicon optoelectronic integrated circuits (OEICs) is described. It is verified that silicon OEICs achieve both high sensitivities and high bandwidths up to the GHz range. Silicon OEICs,therefore, compete successfully with III/V OEICs for low-cost high-volume applications.Results of advanced monolithically integrated photodiodes available in CMOS and BiCMOS technologies are presented. The technological aspects for the monolithic integration of photodiodes are addressed and the properties of the so-called double photodiode and of the pin photodiode are described. The innovative integrated double photodiode allowing data rates of 622 Mb/s is available in standard silicon technologies without any process modification. For the integration of the pin photodiode allowing data rates of higher than 1 Gb/s usually at least one additional mask is required. It will be shown that the pin photodiode also can be implemented without an additional mask. The second main part of this article covers circuits of optical fiber and interconnect receivers with data rates of up to 1 Gb/s as well as advanced DVD pick-up OEICs with bandwidths of up to 150 MHz. The fiber receivers achieve an effective transimpedance of 45.9 k(Omega) and the sensitivity of this OEIC in a 1.0 micrometers CMOS technology with a data rate of 1 Gb/s is improved by 9 dB compared to that of a published OEIC in a 0.35 micrometers CMOS technolgy.

A 20V submicron BCDMOS process is presented with extended LDMOS SOA (Safe-Operating-Area) for smart power applications by optimizing body-current. The LDMOS has two peaks of body current and the origin of two peaks can be explained through hot carrier injection phenomenon. The first peak shows the appearance of weakly impact ionization related to the device degradation and the second peak shows the occurrence of snap-back phenomenon predicting device destruction, respectively. In the present paper, we investigated the HE-SOA (Hot-Electron-Limited SOA) and Electrical SOA using two peaks of body current in LDMOS transistors with submicron BCD process.

Using a newly developed double-side fabrication method, an IJJ stack plus a bow-tie antenna and chokes were integrated in a slice 200 nm thick and singled out from inside a bulk Bi₂Sr₂CaCu₂O_8+x (BSCCO) single crystal. The junctions in the fabricated stack were very uniform, and the number of junctions involved was rather controllable. In addition to this method, which can be used to fabricate integrated circuits based on intrinsic Josephson junctions in high temperature (T_c) superconductors, also reported will be terahertz responses of IJJs, and the possible applications in quantum voltage standard, spectroscopy, and so on.

A new model for electrical low frequency noise in semiconductor heterostructure laser diodes is developed based on number fluctuation theory. The model includes carrier number fluctuation mechanisms such as thermal activation, tunneling and random walk involving bulk traps and interface traps at the heterojunction interface. Noise sources in heterostructure semiconductor laser diodes can be divided into three parts, namely, series resistance including ohmic contacts, p-n junction and the heterojunction. The traps located at the interface and or at the bulk of the barrier layer can induce the modulation of barrier height which in turn results in the current fluctuation. Noise generation mechanisms for p-n junction is reviewed. Correlation between electrical and optical noise is also discussed.

An enhancement mode MESFET (E-MESFET) is useful as a low voltage, low power device and plays an important role in VLSI designing .An E-MESFET behaves as a switch under optical illumination, it turns ON when light is ON and turns OFF when light is switched OFF. Studies have been made on optically controlled characteristics of an ion-implanted GaAs - MESFET which show that the drain source current can be enhanced with increasing photo voltage as well as radiation flux density. Effect of radiation becomes predominant over the impurity concentration. Sharp increase in drain to source current have been observed at flux density greater than or equal to 10²⁰ / m² .

The hydrogenated amorphous carbon (a-C:H) contains significant fractions of sp³ type C bondings, giving them attractive physical and mechanical properties, some similar to a certain extent to the diamond. Otherwise, the dielectric constant of the a-C:H films covers the range of 2.5 - 6, and the a-C:H also can be used for the protective and isolated layer. In this paper, we study the sensitivity of the a-C:H applied to the pH-ISFET (ion sensitive field effect transistor). The a- C:H gate pH-ISFET devices were prepared by the plasma-enhanced low pressure chemical vapor deposition (PE-LPCVD). The sensitivity is determined by the I_DS - V_GS and C-V curves shift in the various pH buffer solutions. We can also measure the pH at zero charge point (pH_pzc) for the a-C:H gate pH-ISFET.

In this paper, the sol-gel prepared SnO₂ thin film is first applied for the pH sensing. We use the SnCl₂(DOT)2H₂O as the precursor. It is cheaper than other methods. The resulting solution is dropped on the gate of the SiO₂ gate pH-ISFET (ion sensitive field effect transistor). After baking, the thin film will convert to SnO₂. We also use the thermal evaporation system to prepare the SnO₂ gate MOSFET. Then, we use the Keithley 236 instrument to measure the I_DS-V_G curves of the SnO₂ gate MOSFET and pH-ISFET for the different pH buffer solutions. Since the MOSFET and pH-ISFET are fabricated on the same silicon wafer, the properties of these devices are identical. Therefore, we can use the experimental results and theoretical model of the pH-ISFET to find the pH sensitivity and pH_PZC (pH at the point of zero charge) of the sol-gel prepared SnO₂ gate pH-ISFET, which are about 57.36 mV/pH and 11.3, respectively.

Various important scientific and engineering applications, such as control of spontaneous emission, zero-threshold lasing, sharp bending of light, and trapping of photons, are expected by using photonic bandgap (PBG) crystals with artificially introduced defect states and/ or light-emitters. Realizing the maximum potential of photonic crystals requires the following steps: (i) construct a three-dimensional (3D) crystal with a complete photonic bandgap in the optical wavelength region; (ii) introduce an arbitrary defect into the crystal at an arbitrary position; (iii) introduce an efficient light-emitter; and, (iv) use an electronically conductive crystal, as this is desirable for actual device application. Although various approaches to constructing 3D crystals have been proposed and investigated, none of these reports satisfies the above requirements simultaneously. To develop complete 3D crystals at infrared (5-10um) to near-infrared wavelengths (1-2um), we stacked III-V semiconductor gratings into a diamond structure by means of wafer bonding and a laser-beam-assisted very precise alignment technique. Since the crystal is constructed with III-V semiconductors, which are widely used for optoelectronic devices, requirement (iii) is satisfied. Moreover, as the wafer bonding enables us to construct an arbitrary structure and to form an electronically conductive interface, all the above requirements (i)-(iv) will be satisfied. In this paper, we review our approach for creating full 3D photonic bandgap crystals at near-infrared wavelengths.

The further increase of the wafer diameter, required for high- volume production of integrated circuits, is combined with an increasing thickness of the wafers. The chip thickness, however, decreases in the same time to about 20 micrometer. Therefore techniques are necessary allowing the thinning of the whole wafer in a time and cost efficient way and with a high accuracy. The actual processing techniques and further trends for wafer thinning are summarized. The most important parameters [final surface structure (roughness), generation of subsurface defects, mechanical stresses] are discussed. Concepts of handling techniques and final processing steps of ultra-thin wafers are presented.

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

The behaviors of optoelectron have a very important effect on the quality of photosensitive material, especially on the formation of image. In this paper, the dielectric spectrum technology is used to measure the behaviors of optoelectron. The curves of the behaviors of optoelectron are obtained. Many properties of the behaviors of the optoelectron are gotten through the detailed analysis of the results of the measurement. The influences of the behaviors of the optoelectron on the formation of image are analyzed primarily. The results obtained in this paper are valuable to the overall comprehension of the photosensitive mechanism of the silver halide materials and the process of the formation of image.

The 3-D axisymmetric, steady flow in a micro-tube with Kn number in the 'slip flow' regime is investigated by analytical method and DSMC (direct simulation Monte Carlo) approach. The analytical formulations are derived by dimensional analysis. Under different pressure ratios of the inlet to outlet, the streamwise velocity, nonlinear pressure distributions and volumetric flow rates along the streamwise direction are obtained analytically, which are compared with those given from DSMC computation. Good agreement was achieved. The causes of deviation in pressure distributions between analytical and DSMC results are discussed in terms of compressibility and rarefaction effects.

The ultrafast emission of nanodiamond powder has been detected with ultrafast fluorescence spectroscopy. The ultrafast emission spectrum has been deconvoluted by the Monte-Carlo method and the results show 2 fast decays as 60ps and 350ps, with weighting about 80 percent and 20 percent of the whole emission intensity respectively. Such fast emission has not been detected under the same experimental condition for the samples of pure and defected bulk diamonds. The reason for such ultrafast process has been discussed.

Even at room temperature, sub-100 ,nm CMOS devices are strongly affected by quantum mechanical effects. In addition to commonly-known energy quantization in the channel, a charge dipole is observed to appear in the poly-gate, which shifts the threshold voltage in a different way from channel quantization. Moreover, due to the multi-dimensional nature of the structure, conventional Schrodinger/Poisson's equation solutions in 1D are no longer adequate for predicting the device characteristics. In this paper, two macroscopic, multi-dimensional quantum transport models, density gradient (DG) and non-equilibrium Green's function (NEGF), are discussed. Validity and application scope are established through comparing to measured data and benchmarking with MIT well-tempered MOSFETs (wtm25 and 90 nm, respectively). It is shown both qualitatively and quantitatively that quantum effects are now required in profile calibration and inverse modeling.

ESD effects in integrated circuits have become a major concern as today's technologies shrink to sub-micron/deep- sub-micron dimensions. The thinner gate oxide and shallower junction depth used in the advanced technologies make them very vulnerable to ESD damages. The advanced techniques like silicidation and STI (shallow trench insulation) used for improving other device performances make ESD design even more challenging. For non-silicided technologies, a certain DCGS (drain contact to gate edge spacing) is needed to achieve ESD hardness for nMOS output drivers and nMOS protection transistors. The typical DCGS values are 4-5um and 2-3um for 0.5um and 0.25um CMOS, respectively. The silicidation reduces the ballast resistance provided by DCGS with at least a factor of 10. As a result, scaling of the ESD performance with device width is lost and even zero ESD performance is reported for standard silicided devices. The device level ESD design is focused in this paper, which includes GGNMOS (gate grounded NMOS) and GCNMOS (gate coupled NMOS). The device level ESD testing including TLP (transmission line pulse) is given. Several ESD issues caused by advanced technologies have been pointed out. The possible solutions have been developed and summarized including silicide blocking, process optimization, back-end ballasting, and new protection scheme, dummy gate/n-well resistor ballsting, etc. Some of them require process cost increase, and others provide novel, compact, and simple design but involving royalty/IP (intellectual property) issue. Circuit level ESD design and layout design considerations are covered. The top-level ESD protection strategies are also given.

Advances in semiconductor technology allow the manufacture of VLSI circuits with millions of transistors. With the increase in chip size and the decrease in layout feature size, yield loss due to manufacturing defects has become a serious problem. To overcome this problem, various defect-tolerant techniques have been developed to reduce the design sensitivity to manufacturing defects. This paper reviews techniques for yield enhancement in compaction, routing, and floorplanning stages of layout design.

The value of mechanical micro-probes and FIB in IC design-debug is well understood. As device dimensions shrink, navigating micro-probes within a light microscope is almost impossible. SEM or FIB, which have higher resolution as well as greater depth of focus, overcome this limitation. FIB is, also, preferred for DUT probe-point creation because its higher milling resolution capability can provide better access to lower level metallizations. IC-card chips present an unique challenge; the backside of these are often insulated so grounding must occur on the exposed front-side. Further, because these IC-card chips are small, very careful setups are required before undertaking FIB modifications. Micro-probes within the FIB chamber solved this problem. Three micro-probes were used to stimulate the chip (input-clock, ground and power) with a fourth probe used to measure output nodes. Requested FIB modifications, including rewiring of poly-silicon traces, were completed. Contacting poly-silicon requires FIB-assisted XeF₂ etching through the inter-level dielectric and both fast termination and removal of XeF₂ from the chamber upon poly-silicon exposure. The technique for exposing poly-silicon is described in detail. The synergy of mechanical micro-probes within the FIB chamber benefited both techniques in the design-debug task. We summarize various IC-card packaging styles and requirements to ground, micro-probe, and establish a debug platform.

Closed loop waveform acquisition methods on electron-beam probe systems have been used for many years. Its stability and linearity make it reliable and accurate to quantitatively measure the voltage at a probe point on the device under test (DUT). However, the feedback loop keeps decreasing the charging current to the integrator hence slowing the acquisition process. The open loop method can keep the charging current constant so as to speed up the waveform acquisition. Fast acquisition is desirable for productivity and to minimize electron beam induced contamination of the probe-point. By adjusting the loop gain and the filter mesh voltage properly, we developed a method to use the characteristics of the local linearity of S curve to make the open acquisition loop stable and reliable while significantly boosting the acquisition speed. The results show it can be approximately 25 times faster to acquire a waveform from the DUT. Also shown, the open loop method works ideally for measuring small amplitude (<EQ 1 volt) analog signals as well as logic waveforms.

The aim of the paper is to present the estimation of thermal time constants of various substrates of integrated circuits. The investigation leads to unexpected results, which show that materials having good thermal conductivity are recognized as not so good in aspect of thermal dynamics. The theoretical procedure carried out step-by-step leads to unsteady state temperature computation and thermal time constants calculation. It can be helpful for determination whether a chip is able to overcome so big deal of energy dissipated in expected short period of time. The comparison of thermal time constants of substrates or heat sinks made of various materials is included.

F-P optical thin film filter based on glass was designed and built using thin film coating and RIE technology. Photoresist was the sacrificial layer and later was removed by dry etching.

Pb(Zr_xTi_1-x)O₃(PZT) films have excellent ferroelectric, optical, piezoelectric and pyroelectric properties. We prepared PZT thin films by pulsed laser deposition (PLD). A pulsed 3321 mbar KrF excimer laser was used to ablate the bulk targets. In this work, sintered targets of Pb(Zr_0.94Ti_0.06)O₃ is used to deposit ferroelectric film onto YBCO and LAO underlayers at 570 degrees Celsius. The X-ray diffraction (XRD) pattern shows that the PZT film is of the perovskite structure having the remarkable (00k) orientation. The polarization-voltage (P-V) characteristic of the PZT thin film is measured by the Virtual Ground Mode. The remnant polarization and coercive field have been found to be P_r equals 4.7 (mu) C cm^-2 and V_c equals 0.4 V for Pt/YBCO/PZT/ALO.

In this paper we introduce an ultrafast photoconductive (PC) switch made from low-temperature-grown GaAs, which was fabricated for the generation and detection of electric transients in an ultrafast scanning tunneling microscope (USTM) system. The PC switch was manufactured on a quartz glass substrate. This transparent substrate allows illumination ranging from the front side to the backside. The use of quartz glass as the substrate enables also the low loss of the transmission of frequencies up to the THz regime. A coplanar strip line (CPS) was integrated on the PC switch, in order to propagate THz pulse on the transmission line. For a CPS with width and spacing of 10 micrometer and the PC switch with width of 50 micrometer, the dark current between the two electrodes is about 0.1 pA with a switch voltage at 10 V. The obtained PC switch showed linear I-P, I-V characteristics, low noise, high sensitivity, low dark current, and low background current. The USTM measurements show also a full width at half maximum (FWHM) pulse width of 1.3 ps.

This paper presents the design and simulation of a novel acceleration sensor with high accuracy and overload ability. A super-stable structure with quad-beams , which has highly symmetric structure has been designed, and this help to eliminate the errors caused by the change of the dimensions and position of the piezoresistors in structure. At the same time, this structure induces films between the beams to reduce the cross-axis sensitivity. Some holes are made in the films to reduce the vertical rigidity. Thus, the films have little effect on the sensitivity. Besides, the sandwich structure is adopted In this device , the damping of the device is controlled by adjusting the clearances between the caps and the seismic mass ,which can obtain the large bandwidth and good frequency response. The bumps are made on two caps to get high overload ability. The piezoresistors are covered with metal layer to improve the electric performance. The structure made beneficial to the high resolution, low cross-axis sensitivity, high overload and good electric performance of the device.

Ferro-tin can be obtained by way of direct radiation on low grade tin oxide concentrate with high power laser. This is a new method we are seeking after for metallurgy. Laser metallurgical method has such advantages as less investment on equipment, simpler technology, economization in raw materials and non-pollution. It can be possibly developed into a new metallurgical technology.

Due to their high aspect ratios and small tip radii of curvature, carbon nanotubes may be suitable for electron field emission. Great attention has been paid to field emission of nanotubes since their discovery. In this paper we analyze the emission performance of a single close nanotube and the carbon nanotube had been regard as continuous cylinder with a dome-shape cap. The electron field emission of the single close nanotube was obtained and examined in triode configuration. The emission field of nanotube is simulated by the finite element method on the basis of electrostatic and the field emission theory of vacuum microelectronics, and the emission current is calculated from the Fowler-Nordheim equation. Not only the emission current of the nanotube is calculated for different geometrical parameters of nanotubes and for different applied voltage , but also the electron trajectories are demonstrated in this paper. From the simulation results, the influence of the geometrical shape of the nanotube on the emission performance is evaluated and discussed here. The simulated results can provide useful information in the fabrication of a nanotube array for field emission display panels.

The uncooled thermal bolometer is preferred for a thermal imager because of its low cost, high reliability and high performance. The design principle of readout circuits for two-dimensional microbolometer arrays is introduced in this paper. Then the problems occurring during the progress when the signal is read out for a larger scale array are analyzed and the resolved method is introduced. Otherwise, the reason why the form of bi-CMOS circuit is more suitable for the microbolometer readout circuit is explained in the paper. At the end of the paper the nonuniformity of the circuit is simply described.

In this paper, a novel lateral bipolar transistor on silicon on insulator material is proposed. Dual-sidewalls technology, which is used in some vertical bipolar devices, is applied in this transistor. The first poly-Si sidewall decreases parasitic Cbc capacitor to the lowest level. The second insulator sidewall is used to separate high concentration emitter from base. Different sidewall width will result in different width of intrinsic base. That means thin intrinsic base could be easily achieved by adjusting insulator sidewall. There are other key technologies also, such as: angled implantation, self-aligned silicide. Results of processes simulation show that all the processes are available, the expected structure and profiles are controllable. Device simulation gives an excellent performance: f_T is over 30 GHz, DC current gain is over 20. This type of lateral bipolar transistor with high performances should be a potential competitor in RF devices & ICs, and should meet the needs of SOI-BiCMOS ICs.

We present results of transmittance measurements on periodic layers of ZrO₂/SiO₂ at optical frequencies. These one- dimensional photonic band gap materials exhibit transparency bands and a huge stop band at optical frequencies. A unique feature of these dielectric/dielectric photonic band gap (MM- PBG) materials is that the overall reflectance in the stop band may increase as more periods are deposited. The center frequency and width of the stop bands are adjustable and generally depend on the thickness of the layers and the number of ZrO₂/SiO₂ periods. These simple periodic structures have applications as microcavity reflector in microcavity lasers.