Dr. Brandon L. Ward Profile

Dr. Brandon L. Ward

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Publications (4)

Proceedings Article | 24 March 2017 Presentation + Paper

Integrated approach to improving local CD uniformity in EUV patterning

Andrew Liang, Jan Hermans, Timothy Tran, Katja Viatkina, Chen-Wei Liang, Brandon Ward, Steven Chuang, Jengyi Yu, Greg Harm, Jelle Vandereyken, David Rio, Michael Kubis, Samantha Tan, Mircea Dusa, Akhil Singhal, Bart van Schravendijk, Girish Dixit, Nader Shamma, Rich Wise, Sirish Reddy

Proceedings Volume 10143, 1014319 (2017) https://doi.org/10.1117/12.2258192

KEYWORDS: Extreme ultraviolet lithography, Etching, Extreme ultraviolet, Lithography, High volume manufacturing, Stochastic processes, Plasma etching, Reactive ion etching, Plasma enhanced chemical vapor deposition, Focus stacking software, Photomasks

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Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies.

Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development.

Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

Proceedings Article | 1 April 2008 Paper

Advanced OPC and 2D verification for tip engineering using aggressive illuminations

X. Zhang, T. Lukanc, H. Yang, B. Ward

Proceedings Volume 6924, 69241H (2008) https://doi.org/10.1117/12.773021

KEYWORDS: Optical proximity correction, Scanning electron microscopy, Illumination engineering, Resolution enhancement technologies, Bridges, Printing, Aberration correction, Semiconducting wafers, Algorithm development, Manufacturing

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Proceedings Article | 11 April 2007 Paper

Line-edge roughness in 193-nm resists: lithographic aspects and etch transfer

Thomas Wallow, Alden Acheta, Yuansheng Ma, Adam Pawloski, Scott Bell, Brandon Ward, Cyrus Tabery, Bruno La Fontaine, Ryoung-han Kim, Sarah McGowan, Harry Levinson

Proceedings Volume 6519, 651919 (2007) https://doi.org/10.1117/12.712319

KEYWORDS: Line edge roughness, Etching, Photoresist materials, Spatial frequencies, Lithography, Smoothing, Image processing, Critical dimension metrology, Semiconducting wafers, Photoresist processing

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Proceedings Article | 10 May 2005 Paper

Information server test case: the effects of probe current stability on CD-SEM measurement

Susan Redmond, Ron Weller, Richard Tomasco, Bill Keese, Nick Spaniola, Tatsuya Maeda, Kenichi Takenouchi, Lorena Page, Alex Danilevsky, Roger Williams, Daniel Berger, Brandon Ward

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.599062

KEYWORDS: Scanning electron microscopy, Metrology, Optical alignment, Edge detection, Objectives, Local area networks, Silicon, Modulation, Semiconductor manufacturing, Environmental monitoring

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