Mr. Chi-hao Huang Profile

Chi-hao Huang

at Macronix International Co Ltd

SPIE Involvement:

Author

Publications (5)

Proceedings Article | 26 May 2022 Poster + Presentation + Paper

In device overlay control with multiple overlay metrology in 3D-NAND process

Li-Ting Chang, Yu-Lin Liu, Chi-hao Huang, Rishabh Kushwaha, Yen Chun Chuan Sun, Cheng Hung Wu, Shao Chang Cheng, Hsiao Fei Su, Yen Hung Liu, Mars Yang, Elvis Yang, T. H. Yang, K. C. Chen

Proceedings Volume 12053, 120531P (2022) https://doi.org/10.1117/12.2613193

KEYWORDS: Overlay metrology, Single crystal X-ray diffraction, Metrology, Semiconducting wafers, 3D metrology, Control systems, Process modeling, Polishing, Etching, Image processing

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Proceedings Article | 22 February 2021 Poster + Presentation + Paper

Imaging-based overlay metrology optimized by HV-SEM in 3D-NAND process

Yu-Lin Liu, Li-Ting Chang, Chi-Hao Huang, Mars Yang, Elvis Yang, T. H. Yang, K. C. Chen

Proceedings Volume 11611, 116112M (2021) https://doi.org/10.1117/12.2583609

KEYWORDS: Overlay metrology, Optical filters, Semiconducting wafers, Optical testing, Etching, Detection and tracking algorithms, Wafer-level optics, Optical metrology, Metrology, Inspection

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Proceedings Article | 28 March 2017 Paper

CD uniformity control for thick resist process

Chi-hao Huang, Yu-Lin Liu, Weihung Wang, Mars Yang, Elvis Yang, T. H. Yang, K. C. Chen

Proceedings Volume 10145, 101452J (2017) https://doi.org/10.1117/12.2256174

KEYWORDS: Critical dimension metrology, Photoresist processing, Optical lithography, Line edge roughness, Process control, Compact discs, 3D equipment, Manufacturing, Semiconducting wafers, Edge roughness, Modulation, Lithography

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Proceedings Article | 28 March 2017 Paper

Overlay degradation induced by film stress

Chi-hao Huang, Yu-Lin Liu, Shing-Ann Luo, Mars Yang, Elvis Yang, Yung-Tai Hung, Tuung Luoh, T. H. Yang, K. C. Chen

Proceedings Volume 10145, 101451Z (2017) https://doi.org/10.1117/12.2256626

KEYWORDS: Semiconducting wafers, Etching, Overlay metrology, Scanners, Chemical vapor deposition, Semiconductors, Critical dimension metrology, Optical alignment, Lithography, Plasma enhanced chemical vapor deposition, Optical lithography, Mass attenuation coefficient, Oxides

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The semiconductor industry has continually sought the approaches to produce memory devices with increased memory cells per memory die. One way to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories is 3D stacked flash cell array. In constructing 3D NAND flash memories, increasing the number of stacked layers to build more memory cell number per unit area necessitates many high-aspect-ratio etching processes accordingly the incorporation of thick and unique etching hard-mask scheme has been indispensable. However, the ever increasingly thick requirement on etching hard-mask has made the hard-mask film stress control extremely important for maintaining good process qualities. The residual film stress alters the wafer shape consequently several process impacts have been readily observed across wafer, such as wafer chucking error on scanner, film peeling, materials coating and baking defects, critical dimension (CD) non-uniformity and overlay degradation. This work investigates the overlay and residual order performance indicator (ROPI) degradation coupling with increasingly thick advanced patterning film (APF) etching hard-mask. Various APF films deposited by plasma enhanced chemical vapor deposition (PECVD) method under different deposition temperatures, chemicals combinations, radio frequency powers and chamber pressures were carried out. And -342MPa to +80MPa film stress with different film thicknesses were generated for the overlay performance study. The results revealed the overlay degradation doesn’t directly correlate with convex or concave wafer shapes but the magnitude of residual APF film stress, while increasing the APF thickness will worsen the overlay performance and ROPI strongly. High-stress APF film was also observed to enhance the scanner chucking difference and lead to more serious wafer to wafer overlay variation. To reduce the overlay degradation from ever increasingly thick APF etching hard-mask, optimizing the film stress of APF is the most effective way and high order overlay compensation is also helpful.

Proceedings Article | 8 March 2016 Paper

Within-wafer CD variation induced by wafer shape

Chi-hao Huang, Mars Yang, Elvis Yang, T. H. Yang, K. C. Chen

Proceedings Volume 9778, 97783E (2016) https://doi.org/10.1117/12.2216048

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Etching, Temperature metrology, Image processing, Process control, Compact discs, Scanners, Defect detection, Distortion, Diffusion, Optical lithography, Scanning electron microscopy

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In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity.

The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer PEB temperature non-uniformity attributed to wafer warpage is uncorrectable, and the photo-resist profile variation is believed to affect across-wafer etch bias uniformity to some degree.

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