As the semiconductor industry rapidly approaches lithography nodes beyond 3nm, On Product Overlay (OPO) becomes a critical factor in enabling process control and manufacturing yield. The correspondingly tight OPO error budget emphasizes the importance of accurate overlay (OVL) metrology for capturing and tracking ever-smaller processes and patterning variations. In the DRAM memory segment, additional challenges arise in layers around the storage node, where the critical patterning steps are on thick layers with denser patterns than on other layers. A major challenge for optical overlay measurement on storage node layers comes from opaque optical stack materials whose optical properties reduce signal penetration effectiveness. Another key challenge is the high aspect ratio between the stack height and the target pitch, reducing diffraction efficiency and sensitivity. IBO (Image-Based Overlay) studies have shown that long wavelength (WL) improves the measurability of thick layers and significantly improves overlay results. In this paper, it is reported that longer WL (>800nm) can overcome the measurability challenges and achieve accurate results on a DRAM storage node layer. We present how improvements in raw overlay signal (pupil-plane image uniformity) further result in Total Measurement Uncertainty (TMU) and residual improvements over previous baseline solutions. Long WL enables DRAM manufacturers to meet and tighten OPO specifications on thick, storage node layers in their advanced technology architectures.
As the semiconductor industry rapidly approaches the 3nm lithography node, on-product overlay (OPO) requirements have become tighter, which drives metrology performance enhancements to meet the reduction in overlay (OVL) residuals. The utilization of multiple measurement wavelengths in Imaging- Based Overlay (IBO) has increased in the past few years to meet these needs. Specifically, the color per layer (CPL) method allows for optimizing the OVL measurement conditions per layer, including focus, light, wavelength (WL), and polarization customization which enhance the metrology results. CPL is applicable for multiple technology segments (logic, foundry, DRAM, 3D NAND), relevant for different devices (DRAM high stack layers, NAND channel holes, etc.), and can work well for both thin and thick layers for standard and EUV lithography processes. In this paper, we will review the benefits of CPL for multiple DRAM and NAND critical layers. We will describe how CPL can contribute to measurement accuracy by quantifying the OVL residual reduction in comparison to single-wavelength (SWL) measurement conditions.
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