As the semiconductor industry rapidly approaches the 3nm lithography node, on-product overlay (OPO) requirements have become tighter, which drives metrology performance enhancements to meet the reduction in overlay (OVL) residuals. The utilization of multiple measurement wavelengths in Imaging- Based Overlay (IBO) has increased in the past few years to meet these needs. Specifically, the color per layer (CPL) method allows for optimizing the OVL measurement conditions per layer, including focus, light, wavelength (WL), and polarization customization which enhance the metrology results. CPL is applicable for multiple technology segments (logic, foundry, DRAM, 3D NAND), relevant for different devices (DRAM high stack layers, NAND channel holes, etc.), and can work well for both thin and thick layers for standard and EUV lithography processes. In this paper, we will review the benefits of CPL for multiple DRAM and NAND critical layers. We will describe how CPL can contribute to measurement accuracy by quantifying the OVL residual reduction in comparison to single-wavelength (SWL) measurement conditions.
For advanced nodes, a robust metrology is required to estimate EPE and its contributors. Especially when moving to late process development steps (Ramp-Up and High Volume Manufacturing (HVM)) where inter and intra wafer variations are small but crucial. In this study, we used 8um by 8um SEM images to assess the benefit of large Field-of-View (LFOV) metrology. The result proves the capability of LFOV metrology in capturing not only intra-wafer EPE behavior and its sensitivity to minor variations but also the minor wafer-to-wafer (W2W) variations which is not possible using a small FOV (SFOV) metrology (0.5um by 0.5um) due to larger noise level.
In this paper, budget characterization and wafer mapping of the Edge Placement Error (EPE) is studied to manage and improve pattern defects with a use case selected from SK Hynix’s most advanced DRAM 1x nm product. To quantify EPE, CD and overlay were measured at the multiple process steps and then combined for the EPE reconstruction. Massive metrology was used to capture extreme statistics and fingerprint across the wafer. An EPE budget breakdown was performed to identify main contributors and their variations. The end result shows EPEmax is mostly driven by local CD and overlay components while EPE variation is dominated by overlay and global CD components. Beyond EPE budget, a novel EPE wafer mapping methodology is introduced to visualize the temporal and spatial EPE performance which captures variation not seen from CD and overlay. This enables root-cause analysis of the pattern defects, and provides a foundation towards a better process monitoring solution. For EPE improvement, serial CD and overlay optimization simulation was performed to verify opportunities for reduction of the EPE and variation using the available ASML applications. The potential improvement for this use-case was confirmed to be 4.5% compared to baseline performance.
As the scales of the semiconductor devices continue to shrink, accurate measurement and control of the overlay have been emphasized for securing more overlay margin. Conventional overlay analysis methods are based on the optical measurement of the overlay mark. However, the overlay data obtained from these optical methods cannot represent the exact misregistration between two layers at the circuit level. The overlay mismatch may arise from the size or pitch difference between the overlay mark and the real pattern. Pattern distortion, caused by CMP or etching, could be a source of the overlay mismatch as well. Another issue is the overlay variation in the real circuit pattern which varies depending on its location. The optical overlay measurement methods, such as IBO and DBO that use overlay mark on the scribeline, are not capable of defining the exact overlay values of the real circuit. Therefore, the overlay values of the real circuit need to be extracted to integrate the semiconductor device properly. The circuit level overlay measurement using CDSEM is time-consuming in extracting enough data to indicate overall trend of the chip. However DBM tool is able to derive sufficient data to display overlay tendency of the real circuit region with high repeatability. An E-beam based DBM(Design Based Metrology) tool can be an alternative overlay measurement method.
In this paper, we are going to certify that the overlay values extracted from optical measurement cannot represent the circuit level overlay values. We will also demonstrate the possibility to correct misregistration between two layers using the overlay data obtained from the DBM system.
As design rule shrink, overlay has been critical factor for semiconductor manufacturing. However, the overlay
error which is determined by a conventional measurement with an overlay mark based on IBO and DBO often
does not represent the physical placement error in the cell area. The mismatch may arise from the size or pitch
difference between the overlay mark and the cell pattern. Pattern distortion caused by etching or CMP also can
be a source of the mismatch. In 2014, we have demonstrated that method of overlay measurement in the cell
area by using DBM (Design Based Metrology) tool has more accurate overlay value than conventional method
by using an overlay mark. We have verified the reproducibility by measuring repeatable patterns in the cell area,
and also demonstrated the reliability by comparing with CD-SEM data.
We have focused overlay mismatching between overlay mark and cell area until now, further more we have
concerned with the cell area having different pattern density and etch loading. There appears a phenomenon
which has different overlay values on the cells with diverse patterning environment. In this paper, the overlay
error was investigated from cell edge to center. For this experiment, we have verified several critical layers in
DRAM by using improved(Better resolution and speed) DBM tool, NGR3520.
Until recent device nodes, lithography has been struggling to improve its resolution limit. Even though next generation lithography technology is now facing various difficulties, several innovative resolution enhancement technologies, based on 193nm wavelength, were introduced and implemented to keep the trend of device scaling. Scanner makers keep developing state-of-the-art exposure system which guarantees higher productivity and meets a more aggressive overlay specification. “The scaling reduction of the overlay error has been a simple matter of the capability of exposure tools. However, it is clear that the scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieve the desired performance.(2)” In a manufacturing fab, the overlay error, determined by a conventional overlay measurement: by using an overlay mark based on IBO and DBO, often does not represent the physical placement error in the cell area of a memory device. The mismatch may arise from the size or pitch difference between the overlay mark and the cell pattern. Pattern distortion, caused by etching or CMP, also can be a source of the mismatch. Therefore, the requirement of a direct overlay measurement in the cell pattern gradually increases in the manufacturing field, and also in the development level. In order to overcome the mismatch between conventional overlay measurement and the real placement error of layer to layer in the cell area of a memory device, we suggest an alternative overlay measurement method utilizing by design, based metrology tool. A basic concept of this method is shown in figure1. A CD-SEM measurement of the overlay error between layer 1 and 2 could be the ideal method but it takes too long time to extract a lot of data from wafer level. An E-beam based DBM tool provides high speed to cover the whole wafer with high repeatability. It is enabled by using the design as a reference for overlay measurement and a high speed scan system. In this paper, we have demonstrated that direct overlay measurement in the cell area can distinguish the mismatch exactly, instead of using overlay mark. This experiment was carried out for several critical layer in DRAM and Flash memory, using DBM(Design Based Metrology) tool, NGR2170™.
Extreme ultraviolet lithography (EUVL) is one of the most leading lithography technologies for high volume manufacturing. The EUVL is based on reflective optic system therefore critical patterning issues are arisen from the surface of photomask. Defects below and inside of the multilayer or absorber of EUV photomask is one of the most critical issues to implement EUV lithography in mass production. It is very important to pick out and repair printable mask defects. Unfortunately, however, infrastructure for securing the defect free photomask such as inspection tool is still under development furthermore it does not seem to be ready soon. In order to overcome the lack of infrastructures for EUV mask inspection, we will discuss an alternative methodology which is based on wafer inspection results using DBM (Design Based Metrology) tool. It is very challenging for metrology to quantify real mask defect from wafer inspection result since various sources are possible contributor. One of them is random defect comes from poor CD uniformity. It is probable that those random defects are majority of a defect list including real mask defects. It is obvious that CD uniformity should be considered to pick out only a real mask defect. In this paper, the methodology to determine real mask defect from the wafer inspection results will be discussed. Experiments are carried out on contact layer and on metal layer using mask defect inspection tool, Teron(KLA6xx) and DBM (Design Based Metrology) tool, NGR2170™.
Traditional rule-based and model-based OPC methods only simulate in a very local area (generally less than 1um) to identify and correct for systematic optical or process problems. Despite this limitation, however, these methods have been very successful for many technology generations and have been a major reason for the industry being able to tremendously push down lithographic K1. This is also enabled by overall good across-exposure field lithographic process control which has been able to minimize longer range effects across the field. Now, however, the situation has now become more complex. The lithographic single exposure resolution limit with 1.35NA tools remains about 80nm pitch but the final wafer dimensions and final wafer pitches required in advanced technologies continue to scale down. This is putting severe strain on lithographic process and OPC CD control. Therefore, formerly less important 2nd order effects are now starting to have significant CD control impact if not corrected for. In this paper, we provide examples and discussion of how optical and chemical flare related effects are becoming more problematic, especially at the boundaries of large, dense memory arrays. We then introduce a practical correction method for these systematic effects which reuses some of the recent long range effect correcting OPC techniques developed for EUV pattern correction (such as EUV flare). We next provide analysis of the benefits of these OPC methods for chemical flare issues in 193nm lithography very low K1 lithography. Finally, we summarize our work and briefly mention possible future extensions.
With the shrinkage of semiconductor device scales, advanced semiconductor industries face tremendous challenges
in process control. As lithography and etch processes are pushed to get smaller dimensions, the overlay and
wiggling control are hot issues due to the limiting of pattern performance. Many chip makers are using Double
Patterning Technology (DPT) process to overcome design rule limitations but they are also concerned about overlay
control. In DPT process, obtaining accurate overlay data by measuring overlay marks with traditional metrology is
difficult because of the difference of shape and position between cell pattern and overlay marks. Cell to overlay
mark miss-match will occur when there is lens aberration or mask registration error. Therefore, the best way to
obtain accurate overlay data without error is to measure the real cell itself. The overlay of the cell array using DPT
process can be measured by analyzing the relative position of the 2nd exposed pattern to the 1st exposed pattern. But
it is not easy to clearly distinguish a 1st layer and 2nd layer in a patterned cell array image using CD SEM. The
Design Based Metrology (DBM)-system can help identify which cell pattern is a 1st or 2nd layer, so overlay error
between the 1st and 2nd layers at DPT process can be checked clearly. Another noticeable problem in advanced
processing is wiggling. The wiggling of a pattern become severe by the etch process and must be controlled to meet
electrical characteristics of what the semiconductor device requires. The 1st stage of wiggling control is to
understand the level of wiggling which is crucial to device performance. The DBM-system also can be used for
quantification of wiggling by determining specially designed parameters. In this paper we introduce overlay
verification and wiggling quantification through new methodology for advanced memory devices.
As the design rule shrinks down, various techniques such as RET, DFM have been continuously developed and
applied to lithography field. And we have struggled not only to obtain sufficient process window with those
techniques but also to feedback hot spots to OPC process for yield improvement in mass production. OPC
verification procedure which iterates its processes from OPC to wafer verification until the CD targets are met and
hot spots are cleared is becoming more important to ensure robust and accurate patterning and tight hot spot
management.
Generally, wafer verification results which demonstrate how well OPC corrections are made need to be fed back to
OPC engineer in effective and accurate way. First of all, however, it is not possible to cover all transistors in full-chip
with some OPC monitoring points which have been used for wafer verification. Secondly, the hot spots which
are extracted by OPC simulator are not always reliable enough to represent defective information for full-chip.
Finally, it takes much TAT and labor to do this with CD SEM measurement. These difficulties on wafer verification
would be improved by design based analysis. The optimal OPC monitoring points are created by classifying all
transistors in full chip layout and Hotspot set is selected by pattern matching process using the NanoScopeTM, which
is known as a fast design based analysis tool, with a very small amount of hotspots extracted by OPC simulator in
full chip layout. Then, each set is used for wafer verification using design based inspection tool, NGR2150TM. In this
paper, new verification methodology based on design based analysis will be introduced as an alternative method for
effective control of OPC accuracy and hot spot management.
Scanner mismatch has become one of the critical issues in high volume memory production. There are several
components that contribute to the scanner CD mismatch. One of the major components is illumination pupil difference
between scanners. Because of acceleration of dimensional shrinking in memory devices, the CD mismatch became more
critical in electrical performance and process window.
In this work, we demonstrated computational lithography model based scanner matching for sub 3x nm memory devices.
We used ASML XT:1900Gi as a reference scanner and ASML NXT:1950i as the to-be-matched scanner. Wafer
metrology data and scanner specific parameters are used to build a computational model, and determine the optimal
settings by model simulation to minimize the CD difference between scanners. Nano Geometry Research (NGR) was
used as a wafer CD metrology tool for both model calibration and matching result verification. The extracted pupil
parameters from measured source map from both before and after matching are inspected and analyzed. Simulated and
measured process window changes by applying the matching sub-recipe are also evaluated.
As technology node of memory devices is approaching around 30nm, the process window is becoming much
narrower and production yield is getting more sensitive to tiny defects which used to be not, if ever, so critical. So it
would be very hard to expect the same production yield as now in near future.
It is possible to classify wafer defects into systematic and random defects. Systematic defects can be also divided
into design related and process related defects. Narrow process window, generally, is thought to be the source of
these systematic defects and we have to extend process window with Design for Manufacturing (DFM) and control
process variation with Advanced Process Control (APC) to ensure the production yield.
The sensitivity of random defects, however, has something to do with the smaller design rule itself. For example, the
narrower spaces between lines are subject to bridge defects and the smaller lines, to pinch defects.
Die to data base (DB) Design Based Metrology (DBM) has mainly been in use for detecting systematic defects and
feedback to DFM and APC so far. We are trying to extend the application of DBM to random defects control. The conventional defect inspection systems are reaching its highest limit due to the low signal to noise ratio for extremely small feature sizes of below 40nm. It is found that Die to DB metrology tool is capable of detecting small but critical defects with reliability.
KEYWORDS: Optical proximity correction, Metrology, Semiconducting wafers, Inspection, Metals, Error analysis, Process control, OLE for process control, Design for manufacturing, Electronic design automation
Recently several Design Based Metrologies (DBMs) are introduced and being in use for wafer verification. The
major applications of DBM are OPC accuracy improvement, DFM feed-back through Process Window
Qualification (PWQ) and advanced process control. In general, however, the amount of output data from DBM is
normally so large that it is very hard to handle the data for valuable feed-back. In case of PWQ, more than thousands
of hot spots are detected on a single chip at the edge of process window. So, it takes much time and labor to review
and analyze all the hot spots detected at PWQ. Design-related systematic defects, however, will be found repeatedly
and if they can be classified into groups, it would be possible to save a lot of time for the analysis.
We have demonstrated an EDA tool which can handle the large amount of output data from DBM by classifying
pattern defects into groups. It can classify millions of patterns into less than thousands of pattern groups. It has been
evaluated on the analysis of PWQ of metal layer in NAND Flash memory device and random contact hole patterns
in a DRAM device. Also, verification was tuned to specific needs of the designer as well as defect analysis
engineers by use of EDA tool's 'Pattern Matching Function'. The verification result was well within the required
specification of the designer as well as the analysis engineer. The procedures of Hot Spot Management through
Design Based Metrology are presented in detail.
Recently several Design Based Metrologies (DBMs) are introduced and being in use for wafer verification. The
major applications of DBM are OPC accuracy improvement, DFM feed-back through Process Window
Qualification (PWQ) and advanced process control. In general, however, the amount of output data from DBM is
normally so large that it is very hard to handle the data for valuable feed-back. In case of PWQ, more than thousands
of hot spots are detected on a single chip at the edge of process window. So, it takes much time and labor to review
and analyze all the hot spots detected at PWQ. Design-related systematic defects, however, will be found repeatedly
and if they can be classified into groups, it would be possible to save a lot of time for the analysis.
We have demonstrated an EDA tool which can handle the large amount of output data from DBM by reducing
pattern defects to groups. It can classify millions of patterns into less than thousands of pattern groups. It has been
evaluated on the analysis of PWQ of metal layer in NAND Flash memory device and random contact hole patterns
in a DRAM device.
The result shows that this EDA tool can handle the CD measurement data easily and can save us a lot of time and
labor for the analysis. The procedures of systematic defect filtering and data handling using an EDA tool are
presented in detail
During the past few years, new technology brought about new problems we face today due to
shrinkage of the feature size. Some of the problems such as Mask Error Enhancement Factor (MEEF), overlay
control, and so on are crucial because large MEEF can make it difficult to satisfy CD target, and bring about
large CD variation. Moreover, it can also lead to degraded CD uniformity which would have an undesired
influence on device properties. Recently, 2-D random contact hole is getting crucial because it normally has
very large MEEF and cause asymmetric proximity effect which can cause large CD variation, and
misalignment of layer-to-layer. In other words, the method of optical proximity correction and building
accurate OPC model for 2-D random contact hole pattern could be key factor obtaining better CD uniformity
with enhanced overlay margin. Furthermore, in order to get very tangible performance, design based
metrology system (DBM) is used to evaluate process performance. Design based metrology systems are able
to extract information of whole chip CD variation. On top of that, OPC abnormality can be identified and
design feedback can be also disclosed.
In this paper, we will investigate novel method for sub 45nm 2-D random contact hole printing.
First, optical proximity effect (OPE) for two dimensional layout will be investigated. Second, the results of
Variable Threshold Modeling (VTM) for various slit contact hole patterns will be analyzed. Third, model
based verification will be done and analyzed through full-chip before creating full-chip mask. Finally, sub
45nm 2-D random contact hole printing performance will be presented by DBM.
The downscaling of the feature size and pitches of the semi-conductor device requires enough process window and good CDU of exposure field for improvement of device characteristics and high yield. Recently several DBMs (Design Based Metrologies) are introduced for the wafer verification and feed back to for DFM and process control. The major applications of DBM are OPC feed back, process window qualification and advanced process control feed back. With these tools, since the applied tool in this procedure uses e-beam scan method with database of design layout like other ones, more precise and quick verification can be done.
In this work the process window qualification procedure will be discussed in connection with EDA simulation results and then method for obtaining good CDU will be introduced. DoseMapperTM application has been introduced for better field CDU control, but it is difficult to fully correct large field with limited data from normal CD SEM methodology. New DBM has strong points in collecting lots of data required for large field correction with good repeatability (Intra / Inter field).
Generally, rule based optical proximity correction (OPC) together with conventional illumination is used for contact layers, because it is simple to handle and processing times are short. As the design rule is getting smaller, it becomes more difficult to accurately control critical dimension (CD) variation because of influence by nearby contact holes pattern. Especially, random contact hole shows greater amount of CD difference between X and Y direction compared to array contact holes. Several resolution enhancement techniques (RET) were used to resolve this kind of problem, but didn't meet the overall expectations.
In this paper, we will present the results for novel contact hole model-based OPC for sub 60nm memory device. First, model calibration method will be proposed for contact holes pattern, which utilizes two thousands of real contact holes pattern to improve model accuracy in full chip. Second, verification method will be proposed to check weak points on full chip using model based verification. Finally, method for further enhancing CD variation within 5nm for model based OPC will be discussed using Die-to-Database Verification.
KEYWORDS: Semiconducting wafers, Optical proximity correction, Computer aided design, Electronic design automation, Metrology, OLE for process control, Process control, Transistors, Design for manufacturing, Data analysis
Recently several DBMs(Design Based Metrologies) are introduced for the wafer verification and feed back to DFM.
The major applications of DBM are OPC accuracy feed back, process window qualification and advanced process
control feed back. In general, however, DBM brings out huge amount of measurement data and it is necessary to
provide special server system for uploading and handling the raw data. And since it also takes much time and labor
to analyze the raw data for valuable feed back, it is desirable to connect to EDA tools such as OPC tools or
MBV(Model Based Verification) tools for data analysis. If they can communicate with a common language between
them, the DBM measurement result can be sent back to OPC or MBV tools for better model calibration. For
advanced process control of wafer CDU, DBM measurement results of field CDU can be fed back to scanner for
illumination uniformity correction.
In this work, we discuss tool integration of DBM with other tools like EDA tools. These tool integrations are
targeted for the verification procedure automation and as a result for faster and more exact analysis of measurement
data. The procedures of tool integration and automatic data conversion between them will be presented in detail.
K1 factor for development and mass-production of memory devices has been decreased down to below 0.30 in
recent years. Process technology has responded with extreme resolution enhancement technologies (RET) and much
more complex OPC technologies than before. ArF immersion lithography is expected to remain the major patterning
technology through under 35 nm node, where the degree of process difficulties and the sensitivity to process
variations grow even higher. So, Design for manufacturing (DFM) is proposed to lower the degree of process
difficulties and advanced process control (APC) is required to reduce the process variations. However, both DFM
and APC need much feed-back from the wafer side such as hot spot inspection results and total CDU measurements
at the lot, wafer, field and die level.
In this work, we discuss a new design based metrology which can compare SEM image with CAD data and measure
the whole CD deviations from the original layouts in a full die. It can provide the full information of hot spots and
the whole CD distribution diagram of various transistors in peripheral regions as well as cell layout. So, it is possible
to analyze the root cause of the CD distribution of some specific transistors or cell layout, such as OPC error, mask
CDU, lens aberrations or etch process variation and so on. The applications of this new inspection tool will be
introduced and APC using the analysis result will be presented in detail.
As the minimum transistor length is getting smaller, the variation and uniformity of transistor length seriously effect
device performance. So, the importance of optical proximity effects correction (OPC) and resolution enhancement
technology (RET) cannot be overemphasized. However, OPC process is regarded by some as a necessary evil in device
performance. In fact, every group which includes process and design, are interested in whole chip CD variation trend and
CD uniformity, which represent real wafer.
Recently, design based metrology systems are capable of detecting difference between data base to wafer SEM image.
Design based metrology systems are able to extract information of whole chip CD variation. According to the results,
OPC abnormality was identified and design feedback items are also disclosed. The other approaches are accomplished on
EDA companies, like model based OPC verifications. Model based verification will be done for full chip area by using
well-calibrated model. The object of model based verification is the prediction of potential weak point on wafer and fast
feed back to OPC and design before reticle fabrication. In order to achieve robust design and sufficient device margin,
appropriate combination between design based metrology system and model based verification tools is very important.
Therefore, we evaluated design based metrology system and matched model based verification system for optimum
combination between two systems. In our study, huge amount of data from wafer results are classified and analyzed by
statistical method and classified by OPC feedback and design feedback items. Additionally, novel DFM flow would be
proposed by using combination of design based metrology and model based verification tools.
The downscaling of the feature size and pitches of the semi-conductor device requires the improvement of device
characteristics and high yield continuously. In lithography process, RET techniques such as immersion and polarization
including strong PSM mask have enabled this improvement of printability and downscaling of device. It is true that
optical lithography is approaching its limit. So other lithographic technique such as EUV is needed but the application is
not yet available. In this point of view, the realization of lithography friendly layout enables good printability and stable
process. And its scope is being enlarged and applied in most semi-conductor devices. Therefore, in order to realize
precise and effective lithography friendly layout, we need full chip data feedback of design issue, OPC error and
aberration and process variables.
In this paper, we report the results of data feedback using new DFM verification tool. This tool enables full chip
inspection through E-beam scan method with fast and accurate output. And these data can be classified with each item
for correction and stability check through die to database inspection. Especially in gate process, total CD distributions in
full chip can be displayed and analyzed for each target with simple method. At first we obtain accuracy data for each
target and CD uniformity from hundreds of thousands of gate pattern. And second we detect a delicate OPC error by
modeling accuracy and duty difference. It is difficult to get from only measurement of thousands pattern. Finally we
investigated specific pattern and area for electrical characteristic analysis in full chip. These results should be
considered and reflected on design stage.
As the design rule of device shrinks down, it is difficult to enlarge the process window, especially DOF (Depth of Focus). It has shown good results in resolution issues with short wavelength, high NA aperture and several RET (Resolution Enhancement Technique) like special illuminator and mask techniques and so on. But it needs to be challenged for DOF process window in contact / via process having various pitch and pattern location. It is a key point in sub 100nm process development and product. It is demonstrated that focus scan method is effective for DOF improvement in contact and via layers. Focus Scan method is one of the focus drilling techniques; it is realized to tilt wafer stage so that the same point on the wafer field can be exposed in limited continual focus range using multiple focal planes through the slit of scanner tool. In this study, confirmation was inspected for simulation and wafer evaluation for focus scan effects in view of process feasibility. DOF increased over 50% with focus scan in contact mask process even though there are several issues to be solved and considered. Energy Latitude (EL) decreased a little by image contrast drop, but if we consider the process window for evolution of device, it is relatively enough for process. OPC or Bias tuning is needed for application in contact layer having various pitch and location, and overlay issues are needed to confirm for each illuminator. From these experiments, it is found that DOF margin can easily be enhanced using focus scan method. Also some fine tuning is required to adequately use this method on production devices.
In this work, CD control issue at 0.37 K1 optical lithography will be discussed in terms of lens aberration sensitivity. Specific aberration terms that affect CD asymmetry on isolation, word line and storage node layers were investigated by simulation and CD uniformity measurement. The lens aberration was characterized by LITEL ISI (In-Situ Interferometer) and the aberration sensitivity was investigated by Solid-C aerial image simulation. From this result, we can understand the relation between some significant Zernike terms and CD control of DRAM’s critical layers.
One of the crucial factors to take mostly into account the development and production of 130 nm node in low k1 DRAM process is the lens aberration sensitivity control of optical lithographic tools. To meet the required specification these impact of lens aberration resulting from reducing process window caused by pattern deformation, CD uniformity, CD asymmetry, and pattern shift etc. should be understood and considered. In this study, we mainly focused on the aberration sensitivity control for the DRAM isolation layer that is very sensitive to odd components such as coma and three-foil etc. There are a few methods to do this, but the application of extreme sigma setting that is the powerful manner to improvement of asymmetric pattern and layout rotation were examined. It was confirmed that the simulated image and real patterning results for left-right CD difference came from aberrated lens are well matched. In addition, why is the extreme sigma setting more effective than standard settings was investigated with analysis of diffraction patterns on pupil filling of projection lens optics combined with Zernike coefficients phase map.
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