In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher, peripheral circuits may account for more than 50% of the overall chip area. On the contrast, the XtackingTM technology arranges array and logic parts on two different wafers, and connects the memory arrays to the logic circuit by metal VIAs (Vertical Interconnect Accesses) to achieve unprecedented high storage density as well as DRAM level I/O speed. As a consequence, it becomes increasingly significant to monitor metal VIAs depth before wafer bonding process as to ensure reliability of array-logic connections. Currently, AFM (Atom Force Microscopy) is the main stream method of VIA depth monitoring. Apparently, AFM wins the battle of precision, however the low throughput limited its usage in mass production. In order to accomplish the requirement of VLSI production, a WLI (White Light Interferometry) metrology is revisited and a novel neural network assisted method was developed to monitor VIA depth. Basically, there are two major limitations that keep WLI tools from wider use, transparent film impact and diffraction limitation. In this work, realization of neural network is illustrated and inline dishing measurement is achieved with high accuracy and precision.
KEYWORDS: Chemical mechanical planarization, 3D modeling, Manufacturing, Process modeling, Data modeling, Copper, Semiconducting wafers, Back end of line, Chemical vapor deposition, Design for manufacturability
Vertical NAND (3D NAND) designs provide unprecedented improvements in input/output (I/O) performance and storage density, but require additional analysis to ensure manufacturing and market success. While 3D stacked architectures greatly reduce chip area at advanced technology nodes, greater topology uniformity is essential, not only for inter-layers stacking, but also for the chip bonding process. As the link between design and manufacturing, design for manufacturing (DFM) predicts potential manufacturing issues during the design stage, enabling design teams to modify the layout and mitigate the risk. The copper interconnect process can be modeled through multiple process steps, from film stacking, etch, and copper deposition to polishing. The simulated topology of a given design predicts potential risky areas that may be fixed by changing designs or inserting dummy fill prior to manufacturing. This simulation is a useful technique during yield ramp-up, and can shorten the cycle from design to manufacturing. This paper presents a solution for BEOL CMP modeling and analysis on BEOL copper interconnect of a 3D NAND flow.
KEYWORDS: Chemical mechanical planarization, 3D modeling, Data modeling, Front end of line, Calibration, Polishing, Oxides, Manufacturing, Process modeling, Transmission electron microscopy
Chemical-mechanical polishing (CMP) is a key process that reduces chip topography variation during manufacturing. Any variation outside of specifications can cause hotspots, which negatively impact yield. As technology moves forward, especially in memory processes like 3D NAND, high-quality surface planarity is required to overcome manufacturing challenges in each process step. Any topography variation in the front-end-of-line (FEOL) must be taken into consideration, as it may dramatically impact the surface planarity achieved by subsequent manufacturing steps. Rule-based checking of the design is not sufficient to discover all potential CMP hotspots. An accurate FEOL CMP model is necessary to predict design-induced CMP hotspots and optimize the use of dummy fill to alleviate manufacturing challenges. While back-end-of-line (BEOL) CMP modeling technology has matured in recent years, FEOL CMP modeling is still facing multiple challenges. This paper describes how an accurate FEOL CMP model may be built, and how interlayer dielectric (ILD) layer CMP simulations may be used for 3D NAND design improvement. In the example of ILD CMP model validation for a 3D NAND product, it is shown that the model predictions match well with the silicon data and that the model may successfully be used for hotspot prediction in production designs prior to manufacturing.
KEYWORDS: Metrology, Semiconducting wafers, Image processing, Metals, 3D metrology, Atomic force microscopy, Chemical mechanical planarization, 3D image processing, Wafer bonding, Data processing
The 3D NAND (three-dimensional NAND type) has rapidly become the standard technology for enterprise flash memories, and is also gaining widespread use in other applications. Continued manufacturing process improvements are essential in delivering memory devices with higher I/O performance, higher bit density, and lower cost. Current 3D NAND technology involves process steps that form array and peripheral CMOS (Complementary Metal-Oxide-Semiconductor) regions side-by-side, resulting in waste of silicon real estate and film stress compromises, and limits the paths of making advanced 3D NAND devices. An innovative architecture was invented to overcome these challenges by connecting two wafers electrically through millions of metal VIAs (Vertical Interconnect Access) simultaneously across the whole wafer in one process step [1]. A highly accurate and efficient metrology is required to monitor the VIA interface due to the increased process complexity and precision requirements. With the advanced processing of AFM (Atomic Force Microscopy) images, highly accurate and precise measurements have been achieved. An inline pattern-centric metrology solution that is designed for high volume mass production of high-performance 3D NAND is presented in this paper.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.