We have developed an imaging spectroscopic reflectometry (ISR) method based on hyperspectral imaging and deep learning to detect defects in the bottom region of high-aspect-ratio nanostructures. ISR enables fast and non-destructive imaging of the bottom critical dimension (BCD) of channel holes (CHH) on a chip die of vertical NAND (V-NAND). A supervised learning model is built to predict the BCD by associating a pre-measured hyperspectral cube with scanning electron microscopy images after decapsulation of the top of the sample. The BCD predicted by ISR shows a high correlation of R2=0.72 with the actual BCD, and the distribution of CHH not open (NOP) defects on the chip die identified by bright field inspection after decapsulation is consistent with the BCD image obtained by ISR. In addition, ISR can detect defects that occur at arbitrary positions relative to the optical critical dimension (OCD) of the die. On fully integrated V-NAND chips, the ISR result showed a high correlation (R2=0.82) with the failure rate caused by CHH NOP, while the conventional spot OCD showed only R2=0.41. Thus, ISR can be used to optimize the etch process for weak wafer edge regions and to detect defective etch equipment.
We study the effects of annealing temperature on oxide charge trapping near the SiO2/Si interface using time-dependent second harmonic generation (TD-SHG), which is sensitive to charge separation near the interface. The TD-SHG signals are measured in plasma enhanced tetraethyl orthosilicate (PE TEOS) and high density plasma (HDP) oxide films deposited on silicon, respectively, which are typically used as intermetal dielectric (IMD) layers in 3D NAND. After annealing at temperatures ranging from 550 °C to 850 °C, the initial slopes of the TD-SHG signals at t=0, related to the charge trap density, decrease with increasing annealing temperature for PE TEOS, while the signals from HDP oxides show relatively flat curves independent of temperature even in the as-deposited state due to the reduced charge traps. The direction of the interfacial electric field resulting from the charge separation can be interpreted from the sign of the measured slopes. In PE-TEOS oxides annealed above 800 °C, the slope changes to the opposite sign, indicating the dominance of negative charges rather than positive charges. The observed TD-SHG results support previous suggestions that the electron trapping occurs in the carbon-related center of TEOS and appears to be dominant after high temperature annealing.
We developed imaging spectroscopic reflectometry (ISR) based on hyperspectral imaging and deep learning and built it as an in-line facility. After obtaining the reflectance as a hyperspectral cube of the 350 – 1100 nm wavelength region throughout the whole device wafer, dimension of the nanometer-sized structure can be imaged through the supervised learning model. In particular, by including near-IR region in the spectrum, the bottom critical dimension (BCD) of the high-aspect ratio structure such as channel hole (CHH) of the 3D NAND evaluated in this study can be imaged non-destructively and rapidly. After removing the top through decapsulation, the actual BCD was measured by SEM and was linked to the hyperspectral cube to construct a supervised learning model. The BCD predicted through ISR showed a correlation of R2=0.72 with the actual BCD. In addition, the shape of the defect on device chip caused by insufficient etch at the bottom of CHH, obtained by ISR was identical to the inspection image taken after decapsulation. Compared to spot measurement, ISR shows the advantage of being able to capture defects that occur at random locations in the device wafer. From our high volume sample of 3D NAND, ISR result showed a high correlation (R2 = 0.82) with the rate of failure caused by channel hole while the conventional spot measurement showed only R2 = 0.41. By using ISR, we could optimize the etching process for the wafer edge area where CHH formation is particularly weak.
As the measurability (sampling capacity, measurement coverage, and measurement speed) of metrology systems are being enhanced to keep pace with the evolution of semiconductor manufacturing processes, the detection of defective areas and hidden weak patterns by analyzing the massive measurement data is becoming significantly important. In this study, we propose new methods to detect defective areas and hidden weak patterns by mathematically processing massive measurement data. By applying the methods we propose, we were able to successfully detect the hidden weak signals of the millimeter scale in the wafer.
In case the process margin of the device is large and the defect tendency in the wafer occurs randomly, process monitoring were possible using limited sampling measurement values. Previous 3D structure metrology equipment (CD-SEM, ellipsometry, etc.) are not able to measure the entire structure of the wafer due to the speed limit. If the measurement location does not include a weak point, an error occurs in predicting the wafer defect rate. In this study, we propose a new method that can extract weak points from color maps obtained by high-speed inspection tools that can measure the entire wafer. We were able to reduce the process error by about 20% by weak point monitoring.
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