We have developed an imaging spectroscopic reflectometry (ISR) method based on hyperspectral imaging and deep learning to detect defects in the bottom region of high-aspect-ratio nanostructures. ISR enables fast and non-destructive imaging of the bottom critical dimension (BCD) of channel holes (CHH) on a chip die of vertical NAND (V-NAND). A supervised learning model is built to predict the BCD by associating a pre-measured hyperspectral cube with scanning electron microscopy images after decapsulation of the top of the sample. The BCD predicted by ISR shows a high correlation of R2=0.72 with the actual BCD, and the distribution of CHH not open (NOP) defects on the chip die identified by bright field inspection after decapsulation is consistent with the BCD image obtained by ISR. In addition, ISR can detect defects that occur at arbitrary positions relative to the optical critical dimension (OCD) of the die. On fully integrated V-NAND chips, the ISR result showed a high correlation (R2=0.82) with the failure rate caused by CHH NOP, while the conventional spot OCD showed only R2=0.41. Thus, ISR can be used to optimize the etch process for weak wafer edge regions and to detect defective etch equipment.
Depth profile of the dopant concentration in silicon substrate has a crucial influence on the electric characteristics that defines the device performance, whereas those profile has only been evaluated by destructive methods, most typically Secondary-Ion Mass Spectrometry (SIMS). We applied Terahertz Emission Spectroscopy (TES) that exploits charge carrier drift within the built-in potential structure to p-n junction structure in order to non-destructively extract the information about carrier dynamics and consequently the dopant profile. We prepared samples composed of Boron doped region as a p-Si and Phosphor doped region as a n-Si with a different p-n junction depth, and the TES evaluation was conducted illuminating the pump beam with the wavelength of 400nm. The obtained signals exhibit a clear difference among each sample in spite of the junction depth difference of as small as 15nm. The depth sensitivity of TES measurement was also investigated by utilizing carrier dynamics simulation, and clearly indicates the sensitivity to dopant depth profile, which is consistent with experimental TES signal. These results suggest that TES technology is very promising as in-line dopant profile measurement tool which is currently unrealistic with existing technologies and expected to greatly enhance the process control capability.
We study the effects of annealing temperature on oxide charge trapping near the SiO2/Si interface using time-dependent second harmonic generation (TD-SHG), which is sensitive to charge separation near the interface. The TD-SHG signals are measured in plasma enhanced tetraethyl orthosilicate (PE TEOS) and high density plasma (HDP) oxide films deposited on silicon, respectively, which are typically used as intermetal dielectric (IMD) layers in 3D NAND. After annealing at temperatures ranging from 550 °C to 850 °C, the initial slopes of the TD-SHG signals at t=0, related to the charge trap density, decrease with increasing annealing temperature for PE TEOS, while the signals from HDP oxides show relatively flat curves independent of temperature even in the as-deposited state due to the reduced charge traps. The direction of the interfacial electric field resulting from the charge separation can be interpreted from the sign of the measured slopes. In PE-TEOS oxides annealed above 800 °C, the slope changes to the opposite sign, indicating the dominance of negative charges rather than positive charges. The observed TD-SHG results support previous suggestions that the electron trapping occurs in the carbon-related center of TEOS and appears to be dominant after high temperature annealing.
We developed imaging spectroscopic reflectometry (ISR) based on hyperspectral imaging and deep learning and built it as an in-line facility. After obtaining the reflectance as a hyperspectral cube of the 350 – 1100 nm wavelength region throughout the whole device wafer, dimension of the nanometer-sized structure can be imaged through the supervised learning model. In particular, by including near-IR region in the spectrum, the bottom critical dimension (BCD) of the high-aspect ratio structure such as channel hole (CHH) of the 3D NAND evaluated in this study can be imaged non-destructively and rapidly. After removing the top through decapsulation, the actual BCD was measured by SEM and was linked to the hyperspectral cube to construct a supervised learning model. The BCD predicted through ISR showed a correlation of R2=0.72 with the actual BCD. In addition, the shape of the defect on device chip caused by insufficient etch at the bottom of CHH, obtained by ISR was identical to the inspection image taken after decapsulation. Compared to spot measurement, ISR shows the advantage of being able to capture defects that occur at random locations in the device wafer. From our high volume sample of 3D NAND, ISR result showed a high correlation (R2 = 0.82) with the rate of failure caused by channel hole while the conventional spot measurement showed only R2 = 0.41. By using ISR, we could optimize the etching process for the wafer edge area where CHH formation is particularly weak.
As the measurability (sampling capacity, measurement coverage, and measurement speed) of metrology systems are being enhanced to keep pace with the evolution of semiconductor manufacturing processes, the detection of defective areas and hidden weak patterns by analyzing the massive measurement data is becoming significantly important. In this study, we propose new methods to detect defective areas and hidden weak patterns by mathematically processing massive measurement data. By applying the methods we propose, we were able to successfully detect the hidden weak signals of the millimeter scale in the wafer.
High integration of semiconductor processes is being made to realize high performance in miniaturized chips. The performance of a semiconductor chip may vary depending on target variables such as thickness, line width, shape, composition, and physical properties of each layer constituting the chip. Therefore, in order to secure chip performance, accurate detection of target variable values and quality control are required, and it is necessary to check in advance for defects that may occur during the process. Optical inspection technology is widely used in the semiconductor metrology field due to its advantage in that it can detect defects in the wafer at high speed by scanning the wafer with a light source having a specific wavelength band. However, in recent years, the size of defects caused by high integration and miniaturization of semiconductor chip processes is getting smaller, and thus there is a limit to detecting micro defects using conventional optical methods. In this study, we propose an algorithm to improve the defect detection performance by utilizing multi-scan images acquired under various conditions. Using the suggested algorithm, it was confirmed that the SNR (Signal to noise ratio) of the defect of interest was improved by about 99%, and the classification performance for noise was improved by 4 times.
In order to achieve pattern shrinkage of the memory device, the manufacturing process is getting more complicated and the production period is getting longer. Therefore, the methodology of predicting fab-out electrical die sorting (EDS) test results from in-fab metrology (CD, Optical CD, Thickness, etc.) data is becoming increasingly important. In this study, we propose a novel methodology to improve the fab-out EDS prediction of memory device with in-fab metrology data. Since fab-out EDS results of memory device are binary data consisting of pass or fail at the chip level, indices based on binary classification are suitable for verifying correlation between in-fab metrology data to fab-out EDS results. However, in memory device production, the number of pass chips is much larger than that of fail chips. So in this case, the data imbalance of the pass/fail chip ratio in memory semiconductor production can lead to distortion of binary classification indices such as accuracy, precision, recall, and F-score. We modified the accuracy equation of binary classification to compensate for distortion of binary classification indices due to data imbalance, allowing us to determine chip-level in-fab production specifications (specs) more accurately. We also confirm that the fab-out EDS prediction error has decreased 37.5% when using new in-fab production specs determined by our effective accuracy equation.
KEYWORDS: Semiconductors, Inspection, Data processing, Semiconductor manufacturing, Scanning electron microscopy, New and emerging technologies, High volume manufacturing
Historically, the development of high-density ICs has been a series of challenges, and we have overcame them and finally succeeded in mass production. However, the time from initiating product development to mass production is increasing, and moreover, it is taking longer than ever to reach maximum production yields. In this manufacturing environment, reducing development and yield ramping-up time is the most important factor in maximizing productivity and profit, and the key solution for this is MI technology. However, in order to respond to next-generation semiconductor products based on complex 3D structures, MI technology is going beyond the requirements especially for highly localized and non-destructive monitoring of 3D profiles. In this paper, we will discuss the evolutionary direction of these MI solutions. First, we will define the MI challenges that come along with the structural difficulties of new product, and review the changes in technology that have evolved in each field to overcome them. We will also explore the limitations of these technologies and see what new methodologies can be nominated to overcome them. We'll also look at what technical elements are required for HVM and what lessons can be learned from the examples in real production. Finally, we will propose how semiconductor MI technology should change its role through new innovations.
In case the process margin of the device is large and the defect tendency in the wafer occurs randomly, process monitoring were possible using limited sampling measurement values. Previous 3D structure metrology equipment (CD-SEM, ellipsometry, etc.) are not able to measure the entire structure of the wafer due to the speed limit. If the measurement location does not include a weak point, an error occurs in predicting the wafer defect rate. In this study, we propose a new method that can extract weak points from color maps obtained by high-speed inspection tools that can measure the entire wafer. We were able to reduce the process error by about 20% by weak point monitoring.
The era of big data and cloud computing services has driven the demand for higher capacity and more compact semiconductor devices. As a result, semiconductor devices are moving from 2-D to 3-D. Most notably, threedimensional (3D) NAND flash memory is the most successful 3D semiconductor device today. 3D NAND overcomes the spatial limitation of conventional planar NAND by stacking memory cells vertically. Since hundreds of vertically stacked semiconductor materials become the channel length in the final product, accurate thickness characterization is critical. In this paper, we propose a non-destructive multilayer thickness characterization method using optical measurements and machine learning. For a silicon oxide/nitride multilayer stack of <200 layers, we could predict the thickness of each layer with an average root-mean-square error (RMSE) of 1.6 Å . In addition, we could successfully classify normal and outlier devices using simulated data. We expect this method to be highly suitable for semiconductor fabrication processes.
In semiconductor industry, fast and effective measurement of pattern variation has been key challenge for assuring massproduct quality. Pattern measurement techniques such as conventional CD-SEMs or Optical CDs have been extensively used, but these techniques are increasingly limited in terms of measurement throughput and time spent in modeling. In this paper we propose time effective pattern monitoring method through the direct spectrum-based approach. In this technique, a wavelength band sensitive to a specific pattern change is selected from spectroscopic ellipsometry signal scattered by pattern to be measured, and the amplitude and phase variation in the wavelength band are analyzed as a measurement index of the pattern change. This pattern change measurement technique is applied to several process steps and verified its applicability. Due to its fast and simple analysis, the methods can be adapted to the massive process variation monitoring maximizing measurement throughput.
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