Dr. Victor Moroz Profile

Dr. Victor Moroz

Scientist at Synopsys Inc

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Publications (6)

Proceedings Article | 22 February 2021 Presentation + Paper

Extending materials to systems co-optimizationTM (MSCOTM) modeling to memory array simulation

Ashish Pal, Plamen Asenov, El Mehdi Bazizi, Jaehyun Lee, Benjamin Colombeau, Sanjay Natarajan, Blessy Alexander, Buvna Ayyagari-Sangmalli, Victor Moroz, Xi-Wei Lin

Proceedings Volume 11614, 116140G (2021) https://doi.org/10.1117/12.2583923

KEYWORDS: Systems modeling, Fin field effect transistors, Logic, TCAD, Standards development, Signal generators, Resistance, Metals, Materials processing, Field effect transistors

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Proceedings Article | 23 March 2020 Presentation + Paper

DTCO acceleration to fight scaling stagnation

Lars Liebmann, Daniel Chanemougame, Peter Churchill, Jonathan Cobb, Chia-Tung Ho, Victor Moroz, Jeffrey Smith

Proceedings Volume 11328, 113280C (2020) https://doi.org/10.1117/12.2554025

KEYWORDS: Fin field effect transistors, Standards development, Transistors, Clocks, Device simulation, TCAD, Logic, Design for manufacturability

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Proceedings Article | 23 March 2020 Presentation + Paper

Multi-varied implementations with common underpinnings in design technology co-optimization

Kevin Lucas, Victor Moroz, John Kim, Soo-Han Choi, Tim Tsuei

Proceedings Volume 11328, 113280Y (2020) https://doi.org/10.1117/12.2553656

KEYWORDS: Device simulation, Optical lithography, Silicon, Semiconducting wafers, Process modeling, Visualization, Lithography, Design for manufacturing

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Fueled by higher bandwidth wireless communication and ubiquitous AI, the demand for more affordable and power efficient transistors is accelerating at a time when Dennard scaling is undeniably crawling to a halt. Escalating wafer and design cost are commonly identified as the primary culprits bringing Moore's law to its knees. However, a third component: the cost of making the wrong technology choice early in the development cycle, is equally responsible for slowing the progress of the semiconductor industry. The enormous complexity of leading edge technology nodes has been achieved incrementally over time by limiting each technology node to mostly small evolutionary steps. Forcing too much innovation in one technology node would have catastrophically disrupted the continuous learning curve. As we approach the fundamental device-physics and material-science limits of dimensional scaling, we are forced to look at far more disruptive device and interconnect innovations to achieve meaningful power-performance-area-cost (PPAC) improvement. For example, the complexity versus benefit tradeoffs of innovative 3-dimensional device architectures with non-standard power-distribution networks are so hard to quantify that rigorous yet efficient prototyping becomes indispensable even prior to committing foundry R&D resources. In this paper we present our work on developing a purpose-built suite of tools to vastly accelerate the quantitative pre-screening and optimization of technology options to help the industry maintain its relentless pace of PPAC scaling. We share several examples that demonstrate how we tune a candidate technology definition with this tool-suite. We also describe the important common technologies in successful Design Technology Co-Optimization (DTCO) flows including physical material and process modeling; electrical and circuit simulation; detailed design analysis and modification to reduce weak points; handling enormous datasets; silicon learning feedback loop and intuitive visualization.

Proceedings Article | 21 March 2012 Paper

Addressing LER through atomistic self-assembly

Victor Moroz, Lars Bomholt

Proceedings Volume 8323, 83231Z (2012) https://doi.org/10.1117/12.916231

KEYWORDS: Line edge roughness, Epitaxy, Lithography, Crystals, Monte Carlo methods, Line width roughness, Etching, Silicon, Transistors

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Proceedings Article | 13 March 2009 Paper

Systematic study of the impact of curved active and poly contours on transistor performance

Victor Moroz, Munkang Choi, Xi-Wei Lin

Proceedings Volume 7275, 72751B (2009) https://doi.org/10.1117/12.814369

KEYWORDS: Transistors, Ions, Shape analysis, Solids, Channel projecting optics, Device simulation, Photomasks, TCAD, Optical proximity correction, Line edge roughness

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Proceedings Article | 29 June 1998 Paper

Optimal proximity correction: application for flash memory design

Y. Chen, D. Huang, K. Sung, J. Chiang, M. Yu, F. Teng, Lung Chu, Juan Rey, Douglas Bernard, Jiangwei Li, Junling Li, V. Moroz, Victor Boksha

Proceedings Volume 3334, (1998) https://doi.org/10.1117/12.310822

KEYWORDS: Photoresist materials, Manufacturing, Etching, Optical lithography, Lithography, Calibration, Photoresist developing, Scanning electron microscopy, 3D modeling, Optics manufacturing

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Showing 5 of 6 publications

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