Design Technology CoOptimization (DTCO) is a mediation process that aims to ensure competitive technology architecture definition while avoiding schedule or yield risks caused by unrealistically aggressive process assumptions. DTCO has evolved from lithography friendly design (LfD) and design for manufacturability (DfM) but differs from these approaches in that the goal is not just to communicate process driven constraints to the designers but to negotiate a more optimal tradeoff between designers’ needs and process developers’ concerns. To achieve a sense of shared ownership and enable innovative solutions, it is important for the process developers to understand the high level goals of the design community. To that end, this short course reviews the fundamental system-on-chip (SoC) design objectives as well as the resulting topological constraints on different building blocks of a SoC, such as standard cells, embedded memories, analog components and place and route flows. The DTCO process is explained as a series of steps that incrementally refine the technology architecture using concepts such as: design driven rules definition, design rule arc analysis, and construct based technology definition. The efficacy of DTCO is illustrated using detailed case-studies at N14 and beyond. As an example of how the communicated material might be applied, the course presents a cautious and very preliminary look at the specific design challenges of scaling to the 7NM node using multiple exposure 193i patterning. It concludes with how holistic DTCO at N7 and beyond is essential to driving profitable scaling by considering process, device, interconnect, circuit and architecture considerations. While it is impossible to present a simple ‘how to’ manual for DTCO, the goal of this course is to break down the abstract concept of DTCO into specific actionable components that collectively play an increasing role in maintaining the industries aggressive pace of semiconductor scaling.

As the need for dimensional scaling continues to outpace the availability of higher resolution patterning solutions, the role of Design for Manufacturability (DfM) is shifting from providing incremental yield enhancement in 65nm and 45nm to becoming the fundamental technology enabler in 32nm and beyond. In parallel, the marketplace and the end customers are demanding high DfM quality at all design levels, from IP components to full chip. This course will cover the most popular manufacturability analysis techniques and their uses in DfM-enhanced design flows at different design phases. Model-based techniques such as critical area analysis, lithography hotspot detection, and CMP thickness prediction will be contrasted to rules-based techniques such as recommended design rules or enhanced routing rules. Differences between iterative DfM techniques such as process aware layout optimization and prescriptive DfM techniques such as regularized layouts and design aware manufacturing will be discussed. The advantages and challenges of introducing manufacturability knowledge early in the design flow will be compared to those of applying manufacturability considerations late. Finally, the most prominent opportunities for innovation in DfM for technology nodes beyond 65nm will be reviewed.

This course provides the attendee with sufficient technical background on Resolution Enhancement Techniques (RET) in optical lithography and Design for Manufacturability (DfM) in VLSI production to be able to appreciate key challenges and opportunities in these rapidly emerging technologies. The course explains fundamental physical principles governing optical lithography in VLSI manufacturing, leading to a solid understanding of RET and their impact on integrated circuit design. Through practical examples and theoretical discussion, the instructors will provide insight into the evolution of DfM and will contrast different DfM approaches for leading edge technology nodes. This course will primarily enable you to put key aspects of the rapidly emerging field of DfM into a solid technical framework to fully appreciate their impact on the IC business. The instructors have been teaching a very popular course on resolution enhancement techniques in optical lithography for the past five years and have now decided to adjust the focus of the course to keep up with industry trends.

Design for Manufacturability (DfM) means different things to different people: those on the design side of our business see it as the art of reducing dimensional and parametric conservatism while protecting aggressive time to market targets, those on the manufacturing side look to DfM to preserve profitability in light of increasing process complexity. Regardless of individual motivations, it is clear that DfM will continue to gain importance as traditional CMOS scaling is rapidly coming to an end. This short course will review the most popular manufacturability analysis techniques and their uses in DfM-enhanced design flows. Model-based techniques such as critical area analysis, lithography hotspot detection, and CMP thickness prediction will be contrasted to rules based techniques such as recommended design rules or enhanced routing rules. Differences between feed-back techniques such as process aware layout optimization and feed-forward techniques such as restricted design rules and design aware manufacturing will be discussed. The advantages and challenges of introducing manufacturability knowledge early in the design flow will be compared to those of applying manufacturability considerations late. Finally, the most prominent opportunities for innovation in DfM for technology nodes beyond 65nm will be reviewed.

Technology scaling beyond 90nm is being challenged both by escalating manufacturability as well as design complexity, forcing the need for deep design-technology co-optimization to maintain profitability and market leadership. As the rapidly growing gap between the available and required lithography resolution is being filled with increasingly complex resolution enhancement techniques (RET), 'lithography friendly design' has to be pursued with a heightened sense of urgency. However, accounting for complex topological restrictions of different RET, dealing with layout specific patterning inaccuracies, preventing yield loss from lithography hotspots, and reacting to various length scales of variability are not enough. Other processes such as chemical mechanical polishing (CMP) and rapid thermal anneal (RTA) are also being pushed to their physical limits and introduce their own set of accuracy, defectivity, and variability challenges. In addition to driving extraordinary process optimization and control efforts in the manufacturing lines, these manufacturability challenges affect design through increasingly complicated design rules, complex design flows, and escalating design margins. This course will review manufacturability challenges in resolution, patterning accuracy, layout correlated defectivity, and variability. It will then explain how these manufacturability challenges affect leading edge logic and memory designs. Finally, three classes of design for manufacturabiliuty solutions: complex and recommended design rules, model-based layout legalization, and ultra-regular layouts using restrictive design rules (RDR) are explained and compared in their effectiveness to maintain profitable scaling to advanced technology nodes.

As the microelectronic industry’s need for dimensional scaling continues to outpace the availability of patterning systems with sufficient resolving power, resolution enhancement techniques (RET) of ever increasing complexity are becoming commonplace. The most severely resolution challenged products competing at the leading edge of the technology roadmap, are relying on lithography friendly designs as a key component of their design for manufacturability (DfM) strategy. This course will explain lithography resolution limits, basic concepts of RET and their layout impact, and optimization techniques for high resolution lithography. The increasing importance of lithography friendly design, however, does not alleviate the need for other DfM techniques addressing random and systematic failure mechanism such as critical area analysis (CAA), layout redundancy, or chemical mechanical polishing (CMP) aware layout optimization. This course will review a variety of process characterization techniques and their uses in DfM. Combining distinctly different DfM techniques into a cohesive optimization solution and then integrating this solution into existing design flows presents its own set of challenges. By reviewing the basic elements of common design flows and exploring how emerging and established DfM solutions affect such flows, this course will convey a broad system level view of an integrated DfM approach.

As the need for dimensional scaling continues to outpace the availability of higher resolution patterning solutions, the role of Design for Manufacturability (DfM) is shifting from providing incremental yield enhancement in 65nm and 45nm to becoming the fundamental technology enabler in 32nm and beyond. This course will cover both these regimes which can be described as ‘soft’ and ‘hard’ DfM. The most popular manufacturability analysis techniques and their uses in DfM-enhanced design flows will be reviewed. Model-based techniques such as critical area analysis, lithography hotspot detection, and CMP thickness prediction will be contrasted to rules based techniques such as recommended design rules or enhanced routing rules. Differences between iterative DfM techniques such as process aware layout optimization and prescriptive DfM techniques such as regularized layouts and design aware manufacturing will be discussed. The advantages and challenges of introducing manufacturability knowledge early in the design flow will be compared to those of applying manufacturability considerations late. Finally, the most prominent opportunities for innovation in DfM for technology nodes beyond 65nm will be reviewed.