Lithographic imaging-driven pattern edge placement errors at the 10-nm node

Jacek K. Tyminski; Julia A. Sakamoto; Shane R. Palmer; Stephen P. Renwick

doi:10.1117/1.JMM.15.2.021402

30 March 2016 Lithographic imaging-driven pattern edge placement errors at the 10-nm node

Jacek K. Tyminski, Julia A. Sakamoto, Shane R. Palmer, Stephen P. Renwick

Author Affiliations +

Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 15, Issue 2, 021402 (March 2016). https://doi.org/10.1117/1.JMM.15.2.021402

Abstract

As new microelectronic designs are being developed, the demands on image overlay and pattern dimension control are compounded by requirements that pattern edge placement errors (EPEs) be at a single-nanometer levels. Scanner performance plays a key role in determining location of the pattern edges at different device layers, not only through overlay but also through imaging performance. The imaging contributes to edge displacement through the variations of the image dimensions and by shifting the images from their target locations. We discuss various aspects of advanced image control relevant to a 10-nm node integrated circuit design. We review a range of issues of pattern edge placement directly linked to pattern imaging. We analyze the impact of different pattern design and scanner-related edge displacement drivers. We present two examples of imaging strategies to pattern logic device metal layer cuts. We analyze EPEs of the cut images resulting from optimized layout design and scanner setup, and we draw conclusions on edge placement control versus imaging performance requirements.

Citation Download Citation

Jacek K. Tyminski, Julia A. Sakamoto, Shane R. Palmer, and Stephen P. Renwick "Lithographic imaging-driven pattern edge placement errors at the 10-nm node," Journal of Micro/Nanolithography, MEMS, and MOEMS 15(2), 021402 (30 March 2016). https://doi.org/10.1117/1.JMM.15.2.021402

Published: 30 March 2016

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