This paper presents the development of a single layer microbolometer pixel fabricated using only ZnO material coated with atomic layer deposition. Due to the stress-free nature and high temperature coefficient of resistance of the ALD coated ZnO material, it can be used both as structural and active layers in microbolometer detectors. The design, simulations, and the fabrication optimization of 35 μm single layer ZnO microbolometers are shown in this study. The designed pixel has a thermal conductance of 3.4x10-7 W/K and a thermal time constant of 1.34 ms while it has a maximum displacement of 0.43 μm under 1000g acceleration. This structure can be used to decrease the design complexities and fabrication costs and increase the yield of the detectors making them possible to be used in low-cost applications.
We propose an all-ZnO bilayer microbolometer, operating in the long-wave infrared regime that can be implemented by consecutive atomic layer deposition growth steps. Bilayer design of the bolometer provides very high absorption coefficients compared to the same thickness of a single ZnO layer. High absorptivity of the bilayer structure enables higher performance (lower noise equivalent temperature difference and time constant values) compared to single-layer structure. We observe these results computationally by conducting both optical and thermal simulations.
The design of two new three-level (3-L) microbolometer structures together with their absorption coefficient optimizations are reported. Three-level microbolometers are the detectors where three sacrificial layers are used during their fabrication process. They are needed to increase the performance of the microbolometer detectors when the lithography and etch-process capabilities of the fabrication facility are limited. Two new 3-L microbolometers are proposed and the absorption simulations of these detectors are performed using a cascaded transmission line model of the detectors. The thermal simulations of the proposed detectors are also done using CoventorWare FEM software. The absorption coefficient of the detectors can be as high as 92%, and their thermal conductance values can be as low as 2.4×10 −8 W/K depending on the type of the detector, resulting in an improvement of 50% on the NETD value when compared with a standard 2-L microbolometer structure fabricated using the same technology. The proposed detector structures can be used to decrease the need for high-process capabilities and make it possible to fabricate high-performance microbolometer detectors especially for universities and research centers.
This paper presents the performance evaluation of a unique method called heating based resistance nonuniformity
compensation (HB-RNUC). The HB-RNUC method utilizes a configurable bias heating duration for each pixel in order
to minimize the readout integrated circuit (ROIC) output voltage distribution range. The outputs of each individual pixel
in a resistive type microbolometer differ from each other by a certain amount due to the resistance non-uniformity
throughout the focal plane array (FPA), which is an inevitable result of the microfabrication process. This output
distribution consumes a considerable portion of the available voltage headroom of the ROIC unless compensated
properly. The conventional compensation method is using on-chip DACs to apply specific bias voltages to each pixel
such that the output distribution is confined around a certain point. However, on-chip DACs typically occupy large
silicon area, increase the output noise, and consume high power. The HB-RNUC method proposes modifying the
resistances of the pixels instead of the bias voltages, and this task can be accomplished by very simple circuit blocks.
The simplicity of the required blocks allows utilizing a low power, low noise, and high resolution resistance nonuniformity
compensation operation. A 9-bit HB-RNUC structure has been designed, fabricated, and tested on a 384x288
microbolometer FPA ROIC on which 35μm pixel size detectors are monolithically implemented, in order to evaluate its
performance. The compensation operation reduces the standard deviation of the ROIC output distribution from 470 mV
to 9 mV under the same readout gain and bias settings. The analog heating channels of the HB-RNUC block dissipate
around 4.1 mW electrical power in this condition, and the increase in the output noise due to these blocks is lower than
10%.
This paper introduces an analysis on the absorption enhancement in uncooled infrared pixels using resonant plasmon
modes in metal structures, and it reports, for the first time in literature, broad-band absorption enhancement using
integrated plasmonic structures in microbolometers for unpolarized long-wave IR detection. Different plasmonic
structures are designed and simulated on a stack of layers, namely gold, polyimide, and silicon nitride in order to
enhance absorption at the long-wave infrared. The simulated structures are fabricated, and the reflectance measurements
are conducted using an FTIR Ellipsometer in the 8-12 μm wavelength range. Finite difference time domain (FDTD)
simulations are compared to experimental measurement results. Computational and experimental results show similar
spectral reflection trends, verifying broad-band absorption enhancement in the spectral range of interest. Moreover, this
paper computationally investigates pixel-wise absorption enhancement by plasmonic structures integrated with
microbolometer pixels using the FDTD method. Special attention is given during the design to be able to implement the
integrated plasmonic structures with the microbolometers without a need to modify the pre-determined microbolometer
process flow. The optimized structure with plasmonic layer absorbs 84 % of the unpolarized radiation in the 8-12 μm
spectral range on the average, which is a 22 % increase compared to a reference structure with no plasmonic design.
Further improvement may be possible by designing multiply coupled resonant structures.
This paper introduces an optimization approach of thermal conductance for single level uncooled microbolometer
detectors. An efficient detector design is required due to the limited availability of silicon area per pixel, i.e., the
pixel pitch, and due to the capabilities of the fabrication line. The trade-offs between physical parameters are studied
to attain the best performance, including the thermal conductance, the thermal time constant, the effective
temperature coefficient of resistance (TCR), and the active area, where the main performance criterion has been
selected as the Noise Equivalent Temperature Difference (NETD). A microbolometer pixel is modeled using
theoretical formulations, and simulations are carried out using this model, and then, the accuracy of the model is
verified by Finite Element Method (FEM) analysis. Consequently, optimum design parameters, such as the length of
the support arms and the choice of interconnect metal can be extracted from the simulations for a defined process
flow. Furthermore, a simple and reliable method for measuring the thermal conductance has been introduced. With
this method, it is possible to accurately measure the thermal conductance in a large pixel temperature range, which is
required especially for high thermal resistance microbolometers as they heat up rapidly in vacuum. The validity and
accuracy of this method are also verified by comparing the simulation results with measurements performed on a
single pixel microbolometer that is designed and fabricated based on the optimization approach outlined in this
paper.
This paper introduces a detailed analysis on the calculation of the absorption coefficient of multilevel uncooled infrared
detectors. The analysis is carried out considering a two-level 25μm pixel pitch infrared detector with a sandwich type resistor
which is divided into sub-regions consisting of different stacks of layers. The absorption coefficients of these different subregions
are calculated individually by using the cascaded transmission line model, including the main body, arms, and the
regions where the resistors are implemented. Then, the total absorption coefficient of the detector is found by calculating the
weighted average of these individual absorption coefficients, where the areas of sub-regions are taken into account. The
absorption can be calculated as a function of the sacrificial and structural layer thicknesses together with the sheet resistance
of the absorber layer to find the optimum value. However, the thermal conductance of the detector must be considered while
adjusting the structural layer thickness. The proposed analysis also takes the thermal conductance into account in order not to
compromise the overall detector performance. Analysis shows that a maximum absorption coefficient of 0.92 for a specific
two-level pixel can be obtained at the 10 μm wavelength, while the pixel results in a time constant of 11.3 ms with 27.2
nW/K thermal conductance in the thermal simulation. It is shown that the absorption coefficient of the pixel is maximized
when the sheet resistance of the absorber is 380 Ω/sheet-resistance, which is almost equal to the free space impedance, as expected.
This paper introduces a new method to estimate the total absorption coefficient of uncooled infrared detectors. Current
approaches in the literature model the infrared detectors as cascaded transmission lines representing the detector layers,
and this model can easily be used to estimate the absorption coefficient if the detector has the same structure at every
point. However, the state of the art uncooled infrared detectors do not have same structure at every point, making it not
feasible to use this simple model. According to the proposed method, the detector structure is divided into subregions
having different layer combinations, and the absorption coefficient of each subregion is calculated separately. Then, the
area ratios of the subregions together with these coefficients are used in order to calculate the total absorption coefficient
of the detector. As the estimation of the absorption coefficient for complex detector structures can easily be done, the
absorption in the required part of the infrared spectrum can be optimized by adjusting the layer properties and layer
thicknesses. This approach can be used both for single and double layer uncooled infrared detector structures.
This paper reports the development of a low-cost 128 x 128 uncooled infrared focal plane array (FPA) based on suspended and thermally isolated CMOS p+-active/n-well diodes. The FPA is fabricated using a standard 0.35 μm CMOS process followed by simple post-CMOS bulk micromachining that does not require any critical lithography or complicated deposition steps; and therefore, the cost of the uncooled FPA is almost equal to the cost of the CMOS chip. The post-CMOS fabrication steps include an RIE etching to reach the bulk silicon and an anisotropic silicon etching to obtain thermally isolated pixels. During the RIE etching, CMOS metal layers are used as masking layers, and therefore, narrow openings such as 2 μm can be defined between the support arms. This approach allows achieving small pixel size of 40 μm x 40 μm with a fill factor of 44%. The FPA is scanned at 30 fps by monolithically integrated multi-channel parallel readout circuitry which is composed of low-noise differential transconductance amplifiers, switched capacitor (SC) integrators, sample-and-hold circuits, and various other circuit blocks for reducing the effects of variations in detector voltage and operating temperature. The fabricated detector has a temperature coefficient of -2 mV/K, a thermal conductance value of 1.8 x 10-7 W/K, and a thermal time constant value of 36 msec, providing a measured DC responsivity (R) of 4970 V/W under continuous bias. Measured detector noise is 0.69 μV in 8 kHz bandwidth at 30 fps scanning rate, resulting a measured detectivity (D*) of 9.7 x 108 cm√HzW. Contribution of the 1/f noise component is found to be negligible due to the single crystal nature of the silicon n-well and its low value at low bias levels. The noise of the readout circuit is measured as 0.76 μV, resulting in an expected NETD value of 1 K when scanned at 30 fps using f=1 optics. This NETD value can be decreased below 350 mK by decreasing the electrical bandwidth with the help of increased number of parallel readout channels and by optimizing the post-CMOS etching steps. The uniformity of the array is very good due to the mature CMOS fabrication technology. The measured uncorrected differential voltage non-uniformity for the 128 x 128 array pixels after the CMOS fabrication is 0.2% with a standard deviation of only 1.5 mV, which is low due to the improved array structure that can compensate for the voltage drops along the routing resistances in the array. Non-uniformity of temperature sensitivity of the array pixels is measured to be less than 3% with a mean and standard deviation of -2.05 mV/K and 61 μV/K, respectively. The temperature sensitivity of the differential pixel voltages has a measured mean value of 2.3 μV/K, relaxing the requirements on the temperature stabilization. Considering its performance and its simple fabrication steps, the proposed method is very cost-effective to fabricate large format focal plane arrays for low-cost infrared imaging applications.
This paper reports the development of a low-cost, small pixel uncooled infrared detector using a standard CMOS process. The detector is based on a suspended and thermally isolated p+-active/n-well diode whose forward voltage changes due to an increase in the pixel temperature with absorbed infrared radiation. The detector is obtained with simple post-CMOS etching steps on dies fabricated using a standard n-well CMOS process. The post-CMOS process steps are achieved without needing any deposition or lithography, therefore, the cost of the detector is almost equal to the cost of the fabricated CMOS chip. Before suspending the pixel using electrochemical etch-stop technique in TMAH, the required etch openings to reach the silicon substrate are created with a simple dry etch process while CMOS metal layers are used as protection mask. Since the etch mask is implemented with available CMOS layers, the etch openings can be reduced significantly, allowing to implement small pixel sizes with reasonable fill factor. This approach is used to implement a 40micrometers x40micrometers diode pixel with a fill factor of 44%, suitable for large format FPAs. The p++)-active/n-well diode has a low 1/f noise, due to its single crystal nature and low bias requirement. Optimum pixel performance is achieved when the pixel is biased at 20(mu) A, where self-heating effect is less than 0.5K. Measurements and calculations show that this new detector has a thermal conductance (Gth) of 1.4E-7W/K and provides a responsivity (R) of 5800V/W and a detectivity (D*) value of 1.9x9cm(root)Hz/W when scanned at 30fps with an electrical bandwidth of 4kHz. If this detector is used to implement a 64x64 or 128x128 FPA with sufficient number of parallel readout channels, these FPAs will provide an NETD value of 195mK considering only the detector noise. When the readout noise is included, these FPAs are expected to provide NETD value below 300mK. Such FPAs are very suitable for ultra low-cost infrared imaging applications.
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