SPIE Journal Paper | 1 January 2011
KEYWORDS: Manufacturing, Tolerancing, Optical proximity correction, Design for manufacturability, Failure analysis, Optics manufacturing, Capacitance, Optical calibration, Clocks, Lithography
Continuous shrinkage of the design rule in large-scale integrated circuit devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension tolerance for each object, considering design intent in terms of electrical behavior, and assigning the tolerance for each process step. However, once the design data are converted to layout data and signed off, most of the design intent is abandoned and unrecognized in the process phase. Thus, uniform and redundant tolerance is used, and therefore, excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intent has been discussed. Using a 40-nm node test chip, electrically critical spots, such as timing, cross-talk noise, electromigration, with small margins are extracted, assigned to the physical layout, and utilized in the manufacturing process. The flow is applicable for optical proximity effect correction (OPC) turnaround time reduction, optimization of OPC/lithography compliance check (LCC) specification, and failure-analysis acceleration. Consequently, a design-intent-aware manufacturing system is promising for realizing proper process specifications and computational cost reduction, in addition to yield enhancement.
