The ongoing scaling of semiconductor devices necessitates increasing development of new and disruptive technologies. Curvilinear layout design and optical proximity correction (OPC) are among the innovations facilitating these advancements in technologies. However, they face challenges in mask enablement technology, including issues with mask writing, data volume management, design complexity, mask data representation, mask qualification, and metrology. In this paper, curvilinear mask test patterns and measurement methodologies are newly proposed for mask qualification and masks specification. Using contour-based mask metrology, edge placement error (EPE), mean-to-target (MTT) and uniformity (CDU) based on target maximum curvature (TMC) are measured and used as the main qualification metrics instead of traditional metrics such as critical dimensions (CD). These novel methods will partly complement standard qualification methods used for non-curvilinear (Manhattan) masks. A set of unique mask test structures are also proposed to extract the minimum set of curvilinear mask rules which enables experimental definition and verification of the manufacturing process.
As semiconductor industry transitions to EUV lithography in advanced technology nodes, EUV stochastic defects play a significant role in chip yield degradation. Present yield models do not account for the stochastic-driven defects that changes by both pitches and critical dimensions (CD) in EUV lithography. In this study, a novel approach that incorporates EUV stochastics into the yield modeling, using calibrated stochastic defects from wafer data is introduced. Then a comparative analysis of yield for various EUV insertion scenarios is meticulously performed. Additionally, strategies to enhance yield in EUV lithography, including CD retargeting are proposed.
The concurrent saturation in dimensional scaling and increase in manufacturing cost and complexity has caused the overall semiconductor manufacturing cost to significantly increase. As a result, the cost per transistor is predicted to sharply increase in future technologies, deviating from the typical 30% cost per transistor reduction. This work explores the use of 3D-integration technologies, as wafer-to-wafer hybrid bonding, for both mobile and high-performance application. It is observed that the use of 3D-integration schemes, can reduce the overall die cost at same functionality, paving the way for cost-effective scaling solutions in future technologies.
KEYWORDS: Extreme ultraviolet, Semiconducting wafers, Photomasks, Fin field effect transistors, Optical lithography, Front end of line, Manufacturing, Back end of line, Yield improvement, Extreme ultraviolet lithography
A yield prediction model with a corresponding cost of the ownership (CoO) and turn-around-time (TAT) analysis is studied on imec’s advanced technology nodes that include EUV and high NA EUV lithography. It also captures device variations from FinFET to CFET. Using modeled die-yield and the cost-of-ownership (CoO) for imec advanced technology nodes including N2, A14, A10, A7 to A5 technology nodes, we show there is a clear correlation trend in choosing a process technology. A precise methodology that can co-model the turn-around-time (TAT) which is inseparable in evaluating the manufacturability is also provided. As a conclusion, node-to-node scalability is proven to be a function of the manufacturability which will be represented to the yield, CoO and TAT metric, not just a function of the patterning complexity or photolithographic resolution that the industry is mainly chasing after.
KEYWORDS: Extreme ultraviolet, Semiconducting wafers, Photomasks, Manufacturing, Optical lithography, Yield improvement, Front end of line, Semiconductor manufacturing, Performance modeling, Back end of line
In semiconductor manufacturing, yield and cost are important factors to predict and improve the productivity of manufactures. A yield prediction model and the corresponding cost of the ownership with advanced technology nodes beyond imec 5nm are proposed in this paper. In this study, the compact die yield data and the cost will be compared between imec 8nm, 7nm and 5nm technology nodes. With technology nodes scaling, the node-to-node scalability can be impacted by the process complexity, different number of layers, and chip size, etc. With proper process parameters, the yield per layer and the yield per chip can be extracted. In addition, the productivity and turn-around-time (TAT), also called cycle time (CT), can also be calculated based on yield and cost model with complex manufacturing process steps to improve the manufacturability and turnaround-time (TAT). The productivity can be easily evaluated by the yield prediction model since productivity and yield are inseparable in manufacturing. Based on the process assumption, the turn-around-time (TAT) can be precisely estimated by the result of the wafer process time including the time of each step provided by the imec database. As the scaling persists, growing complexity in semiconductor manufacturing gives rise to a concern on the yield and cost. We studied a yield model and the corresponding cost of the ownership for imec technology nodes to discuss their manufacturability. With technology nodes progression, the node-to-node scalability is shown to be impacted by the process complexity from the number of layers, patterning methods and chip size, etc. In addition, productivity and turn-aroundtime (TAT), also referred as the cycle time (CT), can also be estimated to be used as an important parameter to enhance productivity and optimize profitability in semiconductor manufacturing.
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