Mr. Olivier Mermet Profile

Olivier Mermet

Engineer at STMicroelectronics SA

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Publications (3)

Proceedings Article | 20 March 2020 Presentation + Paper

Run to run and model variability of overlay high order process corrections for mean intrafield signatures

Benjamin Duclaux, Maxime Gatefait, Olivier Mermet, Jean-Damien Chapon

Proceedings Volume 11325, 113251K (2020) https://doi.org/10.1117/12.2551062

KEYWORDS: Semiconducting wafers, Overlay metrology, Reticles, Scanners, Metrology, Data modeling, Sensors, Data corrections, Process modeling, Performance modeling, Lithographic process control

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Proceedings Article | 20 March 2020 Paper

Mitigating gain, effort and cost for EOW overlay control

Olivier Mermet, Maxime Gatefait, Didier Dabernat, Florent Dettoni, Benjamin Duclaux, Bertrand Le-Gratiet

Proceedings Volume 11325, 113251W (2020) https://doi.org/10.1117/12.2548308

KEYWORDS: Etching, Semiconducting wafers, Scanners, Overlay metrology, Contamination, Lithography, Plasma

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Proceedings Article | 26 March 2019 Presentation + Paper

Investigating process variability at ppm level using advanced massive eBeam CD metrology and contour analysis

B. Le-Gratiet, O. Mermet, C. Gardin, S. Desmoulins, T. Kiers, Y. Wang, P. Tang, D. Tien, F. Wang, C. Prentice, W. Tel, S. Hunsche

Proceedings Volume 10959, 109591A (2019) https://doi.org/10.1117/12.2515242

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Optical lithography, Error analysis, Etching, Scanning electron microscopy, Reliability, Metrology, Control systems, Statistical analysis

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Over the past few years, patterning edge placement error (EPE), which combines information on variability of pattern sizes and placement between adjacent device layers, has been established as the key metric for patterning budget generation and holistic patterning control. More recently, the emergence of high-throughput SEM tools that provide inspection and large-volume CD metrology capabilities has enabled unprecedented statistical analysis of on-product pattern variability.

In the current paper we address edge placement budget generation as well as potential for improved patterning control for an HVM use case at the 28nm litho node. Edge placement and possible related defect mechanisms arise most critically at the contact layer, where contact hole patterning and EPE, with respect to both underlying gate and active layers need to be well controlled. At the 28nm node and for automotive applications, variability control within 5-sigma, i.e. to failure rates below 1 ppm, is generally required to ensure device reliability.

To support generation of an EPE budget by wafer data that captures inter and intra-field components, including local stochastic variations, we use a high-throughput, large field-of-view SEM tool from Hermes Microvision, at all three process layers of interest, as well as YieldStar metrology for overlay characterization. The large volume of data being made available -tens of millions of individual CD measurements- allows mapping out the low-probability ends of variability distributions and detecting non-Gaussian ‘fat tails’ indicative of defect rates that would be underestimated by 3-sigma estimates. Data analysis includes decomposing the total pattern variations into sources of variability, such as global CDU, mask variations and local stochastics. In addition to established CD metrology, we apply novel SEM image based analysis of repetitive patterns in SRAM arrays to generate 2-dimensional process variability bands, including estimates of pattern placement. This approach allows to investigate in detail the probabilistic interaction between active, gate and contact layers.

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