Dr. Ton Kiers Profile

Dr. Ton Kiers

at ASML Netherlands BV

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Author

Publications (16)

Proceedings Article | 22 November 2023 Presentation

Probing EUV resist defect detectability using a SEM simulation framework

Thomas Wallow, Aiqin Jiang, Ton Kiers, Tim Houben, Chris Spence

Proceedings Volume PC12750, PC127500C (2023) https://doi.org/10.1117/12.2687837

KEYWORDS: Scanning electron microscopy, Defect detection, Extreme ultraviolet, Machine learning, Inspection

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Proceedings Article | 26 February 2021 Presentation + Paper

Statistical analysis of the impact of 2D reticle variability on wafer variability in advanced EUV nodes using large-scale Monte Carlo simulations

Adam Lyons, Luke Long, Tom Wallow, Chris Spence, Ton Kiers, Paul van Adrichem, Vidya Vaenkatesan, Jiyou Fu, Christoph Hennerkes, Cyrus Tabery

Proceedings Volume 11609, 116090C (2021) https://doi.org/10.1117/12.2584744

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Proceedings Article | 26 March 2019 Presentation + Paper

Investigating process variability at ppm level using advanced massive eBeam CD metrology and contour analysis

B. Le-Gratiet, O. Mermet, C. Gardin, S. Desmoulins, T. Kiers, Y. Wang, P. Tang, D. Tien, F. Wang, C. Prentice, W. Tel, S. Hunsche

Proceedings Volume 10959, 109591A (2019) https://doi.org/10.1117/12.2515242

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Optical lithography, Error analysis, Etching, Scanning electron microscopy, Reliability, Metrology, Control systems, Statistical analysis

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Over the past few years, patterning edge placement error (EPE), which combines information on variability of pattern sizes and placement between adjacent device layers, has been established as the key metric for patterning budget generation and holistic patterning control. More recently, the emergence of high-throughput SEM tools that provide inspection and large-volume CD metrology capabilities has enabled unprecedented statistical analysis of on-product pattern variability.

In the current paper we address edge placement budget generation as well as potential for improved patterning control for an HVM use case at the 28nm litho node. Edge placement and possible related defect mechanisms arise most critically at the contact layer, where contact hole patterning and EPE, with respect to both underlying gate and active layers need to be well controlled. At the 28nm node and for automotive applications, variability control within 5-sigma, i.e. to failure rates below 1 ppm, is generally required to ensure device reliability.

To support generation of an EPE budget by wafer data that captures inter and intra-field components, including local stochastic variations, we use a high-throughput, large field-of-view SEM tool from Hermes Microvision, at all three process layers of interest, as well as YieldStar metrology for overlay characterization. The large volume of data being made available -tens of millions of individual CD measurements- allows mapping out the low-probability ends of variability distributions and detecting non-Gaussian ‘fat tails’ indicative of defect rates that would be underestimated by 3-sigma estimates. Data analysis includes decomposing the total pattern variations into sources of variability, such as global CDU, mask variations and local stochastics. In addition to established CD metrology, we apply novel SEM image based analysis of repetitive patterns in SRAM arrays to generate 2-dimensional process variability bands, including estimates of pattern placement. This approach allows to investigate in detail the probabilistic interaction between active, gate and contact layers.

Proceedings Article | 20 March 2018 Presentation + Paper

Co-optimization of exposure dose and etch process for SAQP pitch walk control

Mark John Maslow, Vadim Timoshkov, Ton Kiers, Tae Kwon Jee, Liesbeth Reijnen, Kaushik Kumar, Marc Demand, Carlos Fonseca, Florin Cerbu, Guillaume Schelcher, Christophe Beral

Proceedings Volume 10587, 1058704 (2018) https://doi.org/10.1117/12.2297345

KEYWORDS: Etching, Semiconducting wafers, Lithography, Diffractive optical elements, Plasma, Optical lithography, Atomic layer deposition, Critical dimension metrology, Image processing, Deposition processes

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Spacer-assisted pitch multiplication is a patterning technique that is used on many different critical layers for memory and logic devices. Pitch walk can occur when the spacer process, a combination of lithography, deposition and etch processes, produce a repeating, non-uniform grating of space / line CDs. It has been shown that for spacer-assisted double patterning (SADP), where the lithography pitch is doubled, pitch walk can be reduced by controlling the exposure dose such that the uniformity of the final SADP spaces defined by the core resist mandrel (S1) is balanced with the final SADP space defined by the distance between adjacent SADP lines (S2). For higher pitch multiplications, starting with spacer-assisted quadruple patterning (SAQP) reducing systematic pitch walk with exposure dose becomes more complex.

Co-optimization of the lithography and etch processing is expected to be required to achieve the best pitch walk control. Previous work has shown that improving the across wafer CD uniformity of the line patterns after core etch has limited impact on the space CD uniformity after the SADP process, whereas the CD uniformity of the spaces after SAQP did show some dependence. There are additional space populations created by an SAQP process. The variation of these different populations, along with the spacer deposited line populations, is the root cause of the non-uniform grating that results in pitch walk. The complex interactions of the lithography and etch processes’ impact on the CD and profile need to be understood to produce the optimal performance.

Pitch walk is a component of the overall Edge Placement Error (EPE) budget. With current nodes using SAQP for multiple device layers and future nodes expected to continue to implement this patterning technique, minimization of pitch walk variability is an important part of overall patterning optimizations. In this work, we will show how cooptimized exposure dose and etch processes for SAQP patterning can improve pitch walk performance. We will provide a target exposure dose metric for a 32nm pitch SAQP grating. The methodology for achieving the best pitch walk performance by combination of etch process optimization with dose correction will also be shown.

Proceedings Article | 28 March 2017 Paper

Robust 2D patterns process variability assessment using CD-SEM contour extraction offline metrology

Amine Lakcher, Bertrand Le-Gratiet, Julien Ducoté, Pierre Fanton, Ton Kiers, Jan-Willem Gemmink, Stefan Hunsche, Christopher Prentice, Maxime Besacier

Proceedings Volume 10145, 1014514 (2017) https://doi.org/10.1117/12.2257876

KEYWORDS: Etching, Metrology, Lithography, Scanning electron microscopy, Inspection, Process control, Manufacturing, Process engineering, Chemical mechanical planarization, Copper, Semiconducting wafers, Metals, Image processing, Optical alignment

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Proceedings Article | 28 March 2017 Presentation + Paper

CD-SEM distortion quantification for EPE metrology and contour analysis

Harm Dillen, Ton Kiers, Sandip Halder, Thomas Wallow, Frieda van Roey

Proceedings Volume 10145, 1014515 (2017) https://doi.org/10.1117/12.2260664

KEYWORDS: Distortion, Scanning electron microscopy, Metrology, Data corrections, Image quality, Tolerancing, Optical proximity correction, Optical lithography, Visualization, Critical dimension metrology, Data modeling, Semiconducting wafers, Distance measurement, Error analysis, Calibration, Mathematical modeling, Performance modeling

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Proceedings Article | 27 March 2017 Presentation + Paper

Considerations for pattern placement error correction toward 5nm node

Hidetami Yaegashi, Kenichi Oyama, Arisa Hara, Sakurako Natori, Shohei Yamauchi, Masatoshi Yamato, Kyohei Koike, Mark John Maslow, Vadim Timoshkov, Ton Kiers, Paolo Di Lorenzo, Carlos Fonseca

Proceedings Volume 10143, 1014315 (2017) https://doi.org/10.1117/12.2258210

KEYWORDS: Extreme ultraviolet, Lithography, Image processing, Edge roughness, Imaging arrays, Extreme ultraviolet lithography, Line edge roughness, Optical lithography, Critical dimension metrology, Stochastic processes, Etching, Logic, Overlay metrology

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Proceedings Article | 24 March 2017 Presentation + Paper

SAQP and EUV block patterning of BEOL metal layers on IMEC's iN7 platform

Joost Bekaert, Paolo Di Lorenzo, Ming Mao, Stefan Decoster, Stéphane Larivière, Joern-Holger Franke, Victor M. Blanco Carballo, Bogumila Kutrzeba Kotowska, Frederic Lazzarino, Emily Gallagher, Eric Hendrickx, Philippe Leray, R. Ryoung-han Kim, Greg McIntyre, Paul Colsters, Friso Wittebrood, Joep van Dijk, Mark Maslow, Vadim Timoshkov, Ton Kiers

Proceedings Volume 10143, 101430H (2017) https://doi.org/10.1117/12.2258004

KEYWORDS: Optical lithography, Extreme ultraviolet, Back end of line, Metals, Logic, Extreme ultraviolet lithography, Etching, Double patterning technology, Lithography, Photomasks, Stochastic processes, System on a chip, Semiconducting wafers, Critical dimension metrology

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Proceedings Article | 21 March 2017 Presentation + Paper

Co-optimization of lithographic and patterning processes for improved EPE performance

Mark Maslow, Vadim Timoshkov, Ton Kiers, Tae Kwon Jee, Peter de Loijer, Shinya Morikita, Marc Demand, Andrew Metz, Soichiro Okada, Kaushik Kumar, Serge Biesemans, Hidetami Yaegashi, Paolo Di Lorenzo, Joost Bekaert, Ming Mao, Christophe Beral, Stephane Larivière

Proceedings Volume 10149, 101490N (2017) https://doi.org/10.1117/12.2257979

KEYWORDS: Semiconducting wafers, Photoresist processing, Source mask optimization, Overlay metrology

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Complimentary lithography is already being used for advanced logic patterns. The tight pitches for 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns are made using EUV exposures. At the same time, control requirements of CDU, pattern shift and pitch-walk are approaching sub-nanometer levels to meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Local CDU, and Local Placement Error (LPE), are dominant factors in the total Edge Placement error budget. In the lithography process, improving the imaging contrast when printing the core pattern has been shown to improve the local variability. In the etch process, it has been shown that the fusion of atomic level etching and deposition can also improve these local variations. Co-optimization of lithography and etch processing is expected to further improve the performance over individual optimizations alone.

To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.

Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.

Proceedings Article | 20 October 2016 Paper

Translation of lithography variability into after-etch performance: monitoring of golden hotspot

Jo Finders, Ton Kiers, Bertrand Le Gratiet, Amine Lakcher

Proceedings Volume 10032, 100320H (2016) https://doi.org/10.1117/12.2249565

KEYWORDS: Lithography, Scanning electron microscopy, Etching, Semiconducting wafers, Metrology, Line edge roughness, Photomasks, Computer aided design, Process engineering, Optical alignment

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Proceedings Article | 10 May 2005 Paper

Application of optical CD for characterization of 70nm dense lines

Beverly Cheung, Mircea Dusa, Ton Kiers, Hugo Cramer

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.599896

KEYWORDS: Semiconducting wafers, Metrology, Critical dimension metrology, Lithography, Reticles, Wafer-level optics, Scanners, Photoresist materials, Reflectivity, Reflectometry

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Proceedings Article | 10 May 2005 Paper

Scatterometry based 65nm node CDU analysis and prediction using novel reticle measurement technique

Koen van Ingen Schenau, Peter Vanoppen, Hans van der Laan, Ton Kiers, Maurice Janssen

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.601500

KEYWORDS: Reticles, Critical dimension metrology, Scatterometry, Scanning electron microscopy, Sensors, Semiconducting wafers, Photomasks, Phase shifts, Binary data, Scatter measurement

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Proceedings Article | 24 May 2004 Paper

Total test repeatability: a new figure of merit for CD metrology tools

Hugo Cramer, Ton Kiers, Peter Vanoppen, Jeroen Meessen, Frans Blok, Mircea Dusa

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.544249

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Metrology, Scanning electron microscopy, Reticles, Line width roughness, Atrial fibrillation, Scatterometry, Scanners, Lithography

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Proceedings Article | 16 August 2002 Paper

Reticle processing induced proximity effects

Maurice Janssen, Robert de Kruif, Ton Kiers

Proceedings Volume 4764, (2002) https://doi.org/10.1117/12.479335

KEYWORDS: Reticles, Semiconducting wafers, Critical dimension metrology, Etching, Scanning electron microscopy, Manufacturing, Photomasks, Chemical elements, Error analysis, Line edge roughness

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Proceedings Article | 16 July 2002 Paper

Normal-incidence spectroscopic ellipsometry and polarized reflectometry for measurement and control of photoresist critical dimension

James Holden, Thomas Gubiotti, William McGahan, Mircea Dusa, Ton Kiers

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473439

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Scatterometry, Lithography, Metrology, Scatter measurement, Process control, Reflectometry, Data modeling, Spectroscopic ellipsometry

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Proceedings Article | 22 January 2001 Paper

Reticle error correction for lithography tool qualification benefits and limitations

Ton Kiers, Melchior Mulder, Jan van Schoot, Jacques Waelpoel, Robert Uitz

Proceedings Volume 4186, (2001) https://doi.org/10.1117/12.410696

KEYWORDS: Reticles, Atrial fibrillation, Semiconducting wafers, Photomasks, Metrology, Scanners, Lithography, Etching, Pellicles, Laser scattering

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Showing 5 of 16 publications

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