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This sampling tool can use different inputs (production, tools, APC…) in a dynamic way. This means that the system is dynamic for both process and metrology aspects, and can be adapted to integrate different variables and external events. A real time communication flow was created between APC and sampling tool. Even if the measurement skip decision is taken by the sampling tool, the APC feedback is systematically requested when run to run is involved, like for all lithography process steps. The strength is to deal with high products / mix complexity and react in real time to new product introduction, process deviation, atypical lots including R&D projects and sudden change of the products mix. Both tools are so linked that the sampler remains invisible. Process engineers continue to manage and control lithography process through APC tool mainly.
In parallel, different alarms and triggers have been implemented, including a specific “crisis” mode to quickly respond to the metrology equipment loading or availability variability.
The sampler introduction allowed an optimization of the metrology toolset costs and lot cycle time improvement. Also as a consequence, a more efficient metrology control plan, with an optimized balance between process criticality and metrology requirements.
Future opportunities are related to more dynamic behaviors, as a dynamic sampling rate adapted to metrology capacity, function of the real time metrology capacity or sampling decision dynamically based on process variability components.
This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox.
Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.
In the current paper we address edge placement budget generation as well as potential for improved patterning control for an HVM use case at the 28nm litho node. Edge placement and possible related defect mechanisms arise most critically at the contact layer, where contact hole patterning and EPE, with respect to both underlying gate and active layers need to be well controlled. At the 28nm node and for automotive applications, variability control within 5-sigma, i.e. to failure rates below 1 ppm, is generally required to ensure device reliability.
To support generation of an EPE budget by wafer data that captures inter and intra-field components, including local stochastic variations, we use a high-throughput, large field-of-view SEM tool from Hermes Microvision, at all three process layers of interest, as well as YieldStar metrology for overlay characterization. The large volume of data being made available -tens of millions of individual CD measurements- allows mapping out the low-probability ends of variability distributions and detecting non-Gaussian ‘fat tails’ indicative of defect rates that would be underestimated by 3-sigma estimates. Data analysis includes decomposing the total pattern variations into sources of variability, such as global CDU, mask variations and local stochastics. In addition to established CD metrology, we apply novel SEM image based analysis of repetitive patterns in SRAM arrays to generate 2-dimensional process variability bands, including estimates of pattern placement. This approach allows to investigate in detail the probabilistic interaction between active, gate and contact layers.
Process windows are getting tight with a greater and greater contribution of the focus budget. Nanotopography is highly correlated to the chip layout. As a consequence it shows systematic peaks and valleys shifting locally optimum process conditions. Mean, standard deviations and ranges are not enough to characterize it.
It is of high importance to know topography maps to identify care areas on silicon with high risks of defocus situations [2]. These maps can be measured at any process step using PWG (Patterned Wafer Geometry) tools but could also be predicted with models (see proof of concept [3]).
The first part of this paper deals with the development of scripts to extract and express in multiples ways topography information. Different types of expressions will be shown followed by two use cases related to topography description situation: striation detection and slurry choice for CMP. Those two use cases are proofs of concepts showing that data valorization is a path to provide information that can help process engineers to make decisions and save time for defect detection.
This paper ends with a deeper exploration of the correlations between chip designs and nanotopography from an image processing point of view (design layout and wafer topography maps). Short-range and long-range contributions of layouts are used to model nano-topography through a multiple linear regression [4] of the pre-processed design layers densities (surface and perimeter) and wafer topography which is characterized in this work using KLA PWG tooling. The goal being here to predict wafer topography before silicon is being processed so that mitigation solutions can be set up.
PWG metrology tool can measure a full wafer nano-topography map with pixels size of 100μm*100μm which is enough for a focus analysis. Results show that the first model version reaches encouraging figures of 0.77 R2 for a product layer having a 20nm topography range.
Even if the dimensions to consider are higher than in advanced IC nodes, microlenses are sensitive to process variability during lithography and reflow. A good control of the microlens dimensions is key to optimize the process and thus the performance of the final product.
The purpose of this paper is to apply SEM contour metrology [1, 2, 3, 4] to microlenses in order to develop a relevant monitoring methodology and to propose new metrics to engineers to evaluate their process or optimize the design of the microlens arrays.
This work will show that chip topography can be predicted from reticle density and perimeter density data, including experimental proof. Different pixel sizes are used to perform the correlation in-line with the minimum resolution, correlation length of CMP effects and the spot size of the scanner level sensor. Potential applications of the topography determination will be evaluated, including optimizing scanner leveling by ignoring non-critical parts of the field, and without the need for time-consuming offline topography measurements.
The introduction of pitch splitting (Litho-Etch-Litho-Etch) at 14FDSOInm node requires the development of specific metrologies to adopt advanced process control (for CD, overlay and focus corrections). The pitch splitting process leads to final line CD uniformities that are a combination of the CD uniformities of the two exposures, while the space CD uniformities are depending on both CD and OVL variability.
In this paper, investigations of CD and OVL process control of 64nm minimum pitch at Metal1 level of 14FDSOI technology, within the double patterning process flow (Litho, hard mask etch, line etch) are presented.
Various measurements with SEMCD tools (Hitachi), and overlay tools (KT for Image Based Overlay – IBO, and ASML for Diffraction Based Overlay – DBO) are compared. Metrology targets are embedded within a block instanced several times within the field to perform intra-field process variations characterizations.
Specific SEMCD targets were designed for independent measurement of both line CD (A and B) and space CD (A to B and B to A) for each exposure within a single measurement during the DP flow.
Based on those measurements correlation between overlay determined with SEMCD and with standard overlay tools can be evaluated.
Such correlation at different steps through the DP flow is investigated regarding the metrology type. Process correction models are evaluated with respect to the measurement type and the intra-field sampling.
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