Dr. Itty Matthew Profile

Dr. Itty Matthew

Senior Engineer at ASML Silicon Valley

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Publications (6)

Proceedings Article | 30 March 2017 Presentation + Paper

Design intent optimization at the beyond 7nm node: the intersection of DTCO and EUVL stochastic mitigation techniques

Lars Liebmann, Yulu Chen, Vince Plachecki, Nicole Saulnier, Derren Dunn, Itty Matthew, Stephen Hsu, Keith Gronlund, Francis Goodwin, Mohamed Salama, Michael Crouse

Proceedings Volume 10148, 101480H (2017) https://doi.org/10.1117/12.2260865

KEYWORDS: Extreme ultraviolet, Extreme ultraviolet lithography, Stochastic processes, Optical lithography, Lithography, Tolerancing, Computational lithography, Design for manufacturability, Manufacturing, Back end of line, Source mask optimization, Photomasks, Logic, Optical proximity correction, Nanoimprint lithography

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The initial readiness of EUV patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. Thus, Design Technology Co-optimization (DTCO) has become a critical part of technology enablement as scaling has become more challenging and the industry pushes the limits of EUV lithography. The working partnership between the design teams and the process development teams typically involves an iterative approach to evaluate the manufacturability of proposed designs, subsequent modifications to those designs and finally a design manual for the technology. While this approach has served the industry well for many generations, the challenges at the Beyond 7nm node require a more efficient approach. In this work, we describe the use of “Design Intent” lithographic layout optimization where we remove the iterative component of DTCO and replace it with an optimization that achieves both a “patterning friendly” design and minimizes the well-known EUV stochastic effects. Solved together, this “design intent” approach can more quickly achieve superior lithographic results while still meeting the original device’s functional specifications.

Specifically, in this work we will demonstrate “design intent” optimization for critical BEOL layers using design tolerance bands to guide the source mask co-optimization. The design tolerance bands can be either supplied as part of the original design or derived from some basic rules. Additionally, the EUV stochastic behavior is mitigated by enhancing the image log slope (ILS) for specific key features as part of the overall optimization. We will show the benefit of the “design intent approach” on both bidirectional and unidirectional 28nm min pitch standard logic layouts and compare the more typical iterative SMO approach. Thus demonstrating the benefit of allowing the design to float within the specified range. Lastly, we discuss how the evolution of this approach could lead to layout optimization based entirely on some minimal set of functional requirements and process constraints.

Proceedings Article | 16 March 2009 Paper

C-quad polarized illumination for back end thin wire: moving beyond annular illumination regime

Itty Matthew, Bassem Hamieh, Ramya Viswanathan, Sohan Mehta, Derren Dunn, Chidam Kallingal, Hyung-Rae Lee

Proceedings Volume 7274, 72742Y (2009) https://doi.org/10.1117/12.814296

KEYWORDS: Polarization, Line edge roughness, Optical lithography, Semiconducting wafers, Diffraction, Fiber optic illuminators, Fourier transforms, Critical dimension metrology, Lithography, Reticles

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Proceedings Article | 17 October 2008 Paper

Double dipole RET investigation for 32 nm metal layers

Zachary Baum, Derren Dunn, Yi Zou, Zengqin Zhao, Carl Babcock, Pat LaCour, Itty Matthew

Proceedings Volume 7122, 71220R (2008) https://doi.org/10.1117/12.801789

KEYWORDS: SRAF, Optical proximity correction, Resolution enhancement technologies, Photomasks, Critical dimension metrology, Metals, Fiber optic illuminators, Printing, Algorithm development, Detection and tracking algorithms

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Proceedings Article | 22 March 2008 Paper

Characterization of 32nm node BEOL grating structures using scatterometry

Alok Vaid, Matthew Sendelbach, Matthew Angyal, Shahin Zangooie, Pedro Herrera, Itty Matthew, Charles Archie

Proceedings Volume 6922, 69220S (2008) https://doi.org/10.1117/12.773088

KEYWORDS: Copper, Scatterometry, Back end of line, Metals, Critical dimension metrology, Semiconducting wafers, Chemical mechanical planarization, Metrology, Inspection, Dielectrics

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Proceedings Article | 29 March 2006 Paper

Effect of top coat and resist thickness on line edge roughness

Adam Pawloski, Itty Matthew, Anna Minvielle, Lovejeet Singh

Proceedings Volume 6153, 61530W (2006) https://doi.org/10.1117/12.655925

KEYWORDS: Line edge roughness, Thin film coatings, Scanning electron microscopy, Printing, Lithography, Photoresist processing, Photomicroscopy, Immersion lithography, Image processing, Diffusion

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Proceedings Article | 12 May 2005 Paper

Design restrictions for patterning with off-axis illumination

Itty Matthew, Todd Lukanc, Makoto Takahashi, Amada Wilkison, Marina Plat, Cyrus Tabery

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.606444

KEYWORDS: Cadmium sulfide, Optical lithography, Optical proximity correction, Diffraction, Transistors, Critical dimension metrology, Lithography, Photomasks, Resolution enhancement technologies, Lithographic illumination

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Showing 5 of 6 publications

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