For advanced nodes, a robust metrology is required to estimate EPE and its contributors. Especially when moving to late process development steps (Ramp-Up and High Volume Manufacturing (HVM)) where inter and intra wafer variations are small but crucial. In this study, we used 8um by 8um SEM images to assess the benefit of large Field-of-View (LFOV) metrology. The result proves the capability of LFOV metrology in capturing not only intra-wafer EPE behavior and its sensitivity to minor variations but also the minor wafer-to-wafer (W2W) variations which is not possible using a small FOV (SFOV) metrology (0.5um by 0.5um) due to larger noise level.
In this paper, budget characterization and wafer mapping of the Edge Placement Error (EPE) is studied to manage and improve pattern defects with a use case selected from SK Hynix’s most advanced DRAM 1x nm product. To quantify EPE, CD and overlay were measured at the multiple process steps and then combined for the EPE reconstruction. Massive metrology was used to capture extreme statistics and fingerprint across the wafer. An EPE budget breakdown was performed to identify main contributors and their variations. The end result shows EPEmax is mostly driven by local CD and overlay components while EPE variation is dominated by overlay and global CD components. Beyond EPE budget, a novel EPE wafer mapping methodology is introduced to visualize the temporal and spatial EPE performance which captures variation not seen from CD and overlay. This enables root-cause analysis of the pattern defects, and provides a foundation towards a better process monitoring solution. For EPE improvement, serial CD and overlay optimization simulation was performed to verify opportunities for reduction of the EPE and variation using the available ASML applications. The potential improvement for this use-case was confirmed to be 4.5% compared to baseline performance.
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