Mr. Ryoichi Matsuoka Profile

Ryoichi Matsuoka

Design Engineer at Hitachi High-Tech Corp

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Author

Publications (15)

Proceedings Article | 10 April 2013 Paper

SEM-contour shape analysis method for advanced semiconductor devices

Yasutaka Toyoda, Hiroyuki Shindo, Yoshihiro Ota, Ryoichi Matsuoka, Yutaka Hojo, Daisuke Fuchimoto, Daisuke Hibino, Hideo Sakai

Proceedings Volume 8681, 86811K (2013) https://doi.org/10.1117/12.2011459

KEYWORDS: Shape analysis, Distortion, Scanning electron microscopy, Edge detection, Semiconductors, Finite element methods, Optical proximity correction, Error analysis, Image analysis, Semiconducting wafers

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Proceedings Article | 15 March 2012 Paper

Consideration of correlativity between litho and etching shape

Ryoichi Matsuoka, Hiroaki Mito, Shinichi Shinoda, Yasutaka Toyoda

Proceedings Volume 8327, 832710 (2012) https://doi.org/10.1117/12.915785

KEYWORDS: Etching, Optical proximity correction, Semiconducting wafers, Lithography, Photomasks, Metrology, Semiconductors, Inspection, Resolution enhancement technologies, Shape analysis

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Proceedings Article | 25 September 2010 Paper

Study of shape evaluation for mask and silicon using large field of view

Ryoichi Matsuoka, Hiroaki Mito, Shinichi Shinoda, Yasutaka Toyoda

Proceedings Volume 7823, 78232D (2010) https://doi.org/10.1117/12.867756

KEYWORDS: Photomasks, Silicon, Optical proximity correction, Semiconducting wafers, Metrology, Semiconductors, Bridges, Resolution enhancement technologies, Manufacturing, Design for manufacturing

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We have developed a highly integrated method of mask and silicon metrology. The aim of this integration is evaluating the performance of the silicon corresponding to Hotspot on a mask. It can use the mask shape of a large field, besides. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and mask manufacture, and this has a big impact on the semiconductor market that centers on the mask business. As an optimal solution to these issues, we provide a DFM solution that extracts 2-dimensional data for a more realistic and error-free simulation by reproducing accurately the contour of the actual mask, in addition to the simulation results from the mask data. On the other hand, there is roughness in the silicon form made from a mass-production line. Moreover, there is variation in the silicon form. For this reason, quantification of silicon form is important, in order to estimate the performance of a pattern. In order to quantify, the same form is equalized in two dimensions. And the method of evaluating based on the form is popular. In this study, we conducted experiments for averaging method of the pattern (Measurement Based Contouring) as two-dimensional mask and silicon evaluation technique. That is, observation of the identical position of a mask and a silicon was considered. The result proved its detection accuracy and reliability of variability on two-dimensional pattern (mask and silicon) and is adaptable to following fields of mask quality management. •Discrimination of nuisance defects for fine pattern. •Determination of two-dimensional variability of pattern. •Verification of the performance of the pattern of various kinds of Hotspots. In this report, we introduce the experimental results and the application. We expect that the mask measurement and the shape control on mask production will make a huge contribution to mask yield-enhancement and that the DFM solution for mask quality control process will become much more important technology than ever. It is very important to observe the form of the same location of Design, Mask, and Silicon in such a viewpoint. And we report it about algorithm of the image composition in Large Field.

Proceedings Article | 2 April 2010 Paper

Development for 2D pattern quantification method on mask and wafer

Ryoichi Matsuoka, Hiroaki Mito, Yasutaka Toyoda, Zhigang Wang

Proceedings Volume 7638, 76382L (2010) https://doi.org/10.1117/12.846720

KEYWORDS: Photomasks, Silicon, Metrology, Semiconducting wafers, Optical proximity correction, Shape analysis, Semiconductors, Process control, Computer aided design, Inspection

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We have developed the effective method of mask and silicon 2-dimensional metrology. The aim of this method is evaluating the performance of the silicon corresponding to Hotspot on a mask. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and mask manufacture, and this has a big impact on the semiconductor market that centers on the mask business. 2-dimensional Shape quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. On the other hand, there is roughness in the silicon shape made from a mass-production line. Moreover, there is variation in the silicon shape. For this reason, quantification of silicon shape is important, in order to estimate the performance of a pattern. In order to quantify, the same shape is equalized in two dimensions. And the method of evaluating based on the shape is popular. In this study, we conducted experiments for averaging method of the pattern (Measurement Based Contouring) as two-dimensional mask and silicon evaluation technique. That is, observation of the identical position of a mask and a silicon was considered. It is possible to analyze variability of the edge of the same position with high precision. The result proved its detection accuracy and reliability of variability on two-dimensional pattern (mask and silicon) and is adaptable to following fields of mask quality management. - Estimate of the correlativity of shape variability and a process margin. - Determination of two-dimensional variability of pattern. - Verification of the performance of the pattern of various kinds of Hotspots. In this report, we introduce the experimental results and the application. We expect that the mask measurement and the shape control on mask production will make a huge contribution to mask yield-enhancement and that the DFM solution for mask quality control process will become much more important technology than ever. It is very important to observe the shape of the same location of Design, Mask, and Silicon in such a viewpoint.

Proceedings Article | 30 September 2009 Paper

Noble approach for mask-wafer measurement by design-based metrology integration system

Hiroaki Mito, Katsuya Hayano, Tatsuya Maeda, Hiroshi Mohri, Hidetoshi Sato, Ryoichi Matsuoka, Shigeki Sukegawa

Proceedings Volume 7488, 748832 (2009) https://doi.org/10.1117/12.834229

KEYWORDS: Photomasks, Semiconducting wafers, Scanning electron microscopy, System integration, Optical proximity correction, Metrology, Lithography, Manufacturing, Binary data, Data modeling

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OPC technique is getting more complicated toward 32nm and below technology node, i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and then the manufacturing process of them is complicated now. In order to shorten TAT (Turn around time) time, mask technique need be considered in addition to lithography technique. Furthermore, the lens aberration of the exposure system is getting smaller, so the current performance of it is very close to the ideal. On the other hand, when down sizing goes down to 32nm technology node, it starts to be reported that there are cases that size cannot be matched between a mask pattern and the corresponding printed pattern. Therefore, it is very indispensable to understand the pattern sizes correlation between a mask and the corresponding printed wafer in order to improve the accuracy and the quality, in the situation that the device size is so small that low k1 lithography had been developed and widely used in a production. Then it is thought that it is one of the approaches to improve an estimated accuracy of lithography by using contour that was extracted from mask SEM image in addition to mask model. This paper describes a newly developed integration system in order to solve issues above, and the applications. This is a system which integrates CG4500; CD-SEM for mask and CG4000; CD SEM for wafer; using DesignGauge; OPC evaluation system by Hitachi High-Technologies. It was investigated that a measurement accuracy improvement by executing a mask-wafer same point measurement with same measurement algorithm utilizing the new system. At first, we measured patterns described on a mask and verified the validity based on a measurement value, picture, measurement parameter and the coordinate. Then create a job file for a wafer CD-SEM using the system so as to measure the same patterns that were exposed using the mask. In addition, average CD measurement was tried in order to improve the correlation. Also, in order to estimate very accurate pattern shape, a contour was calculated from a mask SEM image, the result and the design data was used in a litho simulation. This realizes verification including mask error. It is thought that it is beneficial for both mask maker and device maker to use this system.

Proceedings Article | 24 March 2009 Paper

New approach for mask-wafer measurement by design-based metrology integration system

Tatsuya Maeda, Katsuya Hayano, Satoshi Kawashima, Hiroshi Mohri, Hideo Sakai, Hiodetoshi Sato, Ryoichi Matsuoka, Makoto Nishihara, Shigeki Sukegawa

Proceedings Volume 7272, 72722D (2009) https://doi.org/10.1117/12.813916

KEYWORDS: Photomasks, Semiconducting wafers, System integration, Scanning electron microscopy, Optical proximity correction, Metrology, Data modeling, Manufacturing, Lithography, Critical dimension metrology

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OPC (Optical Proximity Correction) technique is getting more complicated towards 32 nm technology node and beyond, i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and their manufacturing process is complicated. In order to shorten TAT (Turn around time), mask design technique needs be considered in addition to lithography technique. Furthermore, the lens aberration of the exposure system is getting smaller, so its current performance is very close to the ideal. On the other hand, when down sizing of device feature size reaches the 32nm technology node, cases begin to be reported where the feature dimension is not matched between a mask pattern and the corresponding printed pattern. Therefore, it is indispensable to understand the pattern size correlation between a mask and the corresponding printed wafer in order to improve the processing accuracy and the quality in the situation where the device size is so small that the low k1 lithography is widely used in production. One of the approaches to improve the estimated accuracy of lithography is the use of contour data extracted from mask SEM image in addition to the application of a mask model. This paper describes a newly developed integration system that aims to solve the issues above, and its applications. This is a system that integrates mask CD-SEM (Critical Dimension-Scanning Electron Microscope) CG4500, wafer CD-SEM CG4000, OPC evaluation system DesignGauge, all manufactured by Hitachi High-Technologies. The measurement accuracy improvement was examined by executing a mask-wafer same point measurement, i.e. measurement of the corresponding points, with same measurement algorithm utilizing the new system. First, we measured mask patterns and verified the validity based on the measurement value, the image, the measurement parameter and the coordinates. Then a job file was formulated for a wafer CD-SEM using the new system so as to measure the corresponding patterns that were exposed using the mask. In addition, the average CD measurement was tried in order to improve the capability. Furthermore, in order to estimate the pattern shape with high accuracy, a contour was calculated from a mask SEM image, and the result was used with the design data in a litho simulation. This realizes a verification that includes mask fabrication error. This system is expected to be beneficial for both mask makers and device makers.

Proceedings Article | 13 March 2009 Paper

Integration of mask and silicon metrology in DFM

Ryoichi Matsuoka, Hiroaki Mito, Akiyuki Sugiyama, Yasutaka Toyoda

Proceedings Volume 7275, 72751N (2009) https://doi.org/10.1117/12.816108

KEYWORDS: Photomasks, Silicon, Metrology, Optical proximity correction, Design for manufacturing, Semiconductors, Computer aided design, Lithography, Manufacturing, Edge detection

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We have developed a highly integrated method of mask and silicon metrology. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. We have inspected the high accuracy, stability and reproducibility in the experiments of integration. The accuracy is comparable with that of the mask and silicon CD-SEM metrology. In this report, we introduce the experimental results and the application. As shrinkage of design rule for semiconductor device advances, OPC (Optical Proximity Correction) goes aggressively dense in RET (Resolution Enhancement Technology). However, from the view point of DFM (Design for Manufacturability), the cost of data process for advanced MDP (Mask Data Preparation) and mask producing is a problem. Such trade-off between RET and mask producing is a big issue in semiconductor market especially in mask business. Seeing silicon device production process, information sharing is not completely organized between design section and production section. Design data created with OPC and MDP should be linked to process control on production. But design data and process control data are optimized independently. Thus, we provided a solution of DFM: advanced integration of mask metrology and silicon metrology. The system we propose here is composed of followings. 1) Design based recipe creation: Specify patterns on the design data for metrology. This step is fully automated since they are interfaced with hot spot coordinate information detected by various verification methods. 2) Design based image acquisition: Acquire the images of mask and silicon automatically by a recipe based on the pattern design of CD-SEM.It is a robust automated step because a wide range of design data is used for the image acquisition. 3) Contour profiling and GDS data generation: An image profiling process is applied to the acquired image based on the profiling method of the field proven CD metrology algorithm. The detected edges are then converted to GDSII format, which is a standard format for a design data, and utilized for various DFM systems such as simulation. Namely, by integrating pattern shapes of mask and silicon formed during a manufacturing process into GDSII format, it makes it possible to bridge highly accurate pattern profile information over to the design field of various EDA systems. These are fully integrated into design data and automated. Bi-directional cross probing between mask data and process control data is allowed by linking them. This method is a solution for total optimization that covers Design, MDP, mask production and silicon device producing. This method therefore is regarded as a strategic DFM approach in the semiconductor metrology.

Proceedings Article | 13 March 2009 Paper

High-precision contouring from SEM image in 32-nm lithography and beyond

Hiroyuki Shindo, Akiyuki Sugiyama, Hitoshi Komuro, Yutaka Hojo, Ryoichi Matsuoka, John Sturtevant, Thuy Do, Ir Kusnadi, Germain Fenger, Peter De Bisschop, Jeroen Van de Kerkhove

Proceedings Volume 7275, 72751F (2009) https://doi.org/10.1117/12.814430

KEYWORDS: Calibration, Optical proximity correction, Scanning electron microscopy, Line edge roughness, Edge detection, Algorithm development, Optical alignment, Semiconducting wafers, Data modeling, Critical dimension metrology

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Proceedings Article | 17 October 2008 Paper

New method of 2-dimensional metrology using mask contouring

Ryoichi Matsuoka, Yoshikazu Yamagata, Akiyuki Sugiyama, Yasutaka Toyoda

Proceedings Volume 7122, 71222T (2008) https://doi.org/10.1117/12.802137

KEYWORDS: Photomasks, Optical proximity correction, Metrology, Semiconductors, Edge detection, Computer aided design, Lithography, Profiling, Inspection, Design for manufacturing

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Proceedings Article | 30 October 2007 Paper

New method of contour-based mask-shape compiler

Ryoichi Matsuoka, Akiyuki Sugiyama, Akira Onizawa, Hidetoshi Sato, Yasutaka Toyoda

Proceedings Volume 6730, 67300M (2007) https://doi.org/10.1117/12.746559

KEYWORDS: Photomasks, Optical proximity correction, Edge detection, Computer aided design, Scanning electron microscopy, Profiling, Semiconductors, Design for manufacturing, Image processing, Data modeling

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Proceedings Article | 27 March 2007 Paper

SEM image contouring for OPC model calibration and verification

Cyrus Tabery, Hidetoshi Morokuma, Ryoichi Matsuoka, Lorena Page, George Bailey, Ir Kusnadi, Thuy Do

Proceedings Volume 6520, 652019 (2007) https://doi.org/10.1117/12.714389

KEYWORDS: Calibration, Scanning electron microscopy, Optical proximity correction, Data modeling, Image processing, Edge detection, Process modeling, Metrology, Critical dimension metrology, Image quality

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Lithography models for leading-edge OPC and design verification must be calibrated with empirical data, and this data is traditionally collected as a one-dimensional quantification of the features acquired by a CD-SEM. Two-dimensional proximity features such as line-end, bar-to-bar, or bar-to-line are only partially characterized because of the difficulty in transferring the complete information of a SEM image into the OPC model building process. A new method of two-dimensional measurement uses the contouring of large numbers of SEM images acquired within the context of a design based metrology system to drive improvement in the quality of the final calibrated model. Hitachi High-Technologies has continued to develop "full automated EPE measurement and contouring function" based on design layout and detected edges of SEM image. This function can measure edge placement error everywhere in a SEM image and pass the result as a design layout (GDSII) into Mentor Graphics model calibration flow. Classification of the critical design elements using tagging scripts is used to weight the critical contours in the evaluation of model fitness. During process of placement of the detected SEM edges of into the coordinate system of the design, coordinate errors inevitably are introduced because of pattern matching errors. Also, line edge roughness in 2D features introduces noise that is large compared to the model building accuracy requirements of advanced technology nodes. This required the development of contour averaging algorithms. Contours from multiple SEM images are acquired of a feature and averaged before passing into the model calibration. This function has been incorporated into the prototype Calibre Workbench model calibration flow. Based on these methods, experimental data is presented detailing the model accuracy of a 45nm immersion lithography process using traditional 1D calibration only, and a hybrid model calibration using SEM image contours and 1D measurement results. Error sources in the contouring are assessed and reported on including systematic and random variation in the contouring results.

Proceedings Article | 24 March 2006 Paper

Development of the automatic recipe generation system for CD-SEM using design data

Ryoichi Matsuoka, Atsushi Miyamoto, Wataru Nagatomo, Hidetoshi Morokuma, Takumichi Sutani

Proceedings Volume 6152, 61524N (2006) https://doi.org/10.1117/12.661936

KEYWORDS: Semiconducting wafers, Atrial fibrillation, Scanning electron microscopy, Pattern recognition, Semiconductors, Optical proximity correction, Image acquisition, Image processing, Electronic design automation, Data acquisition

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Proceedings Article | 10 May 2005 Paper

A new matching engine between design layout and SEM image of semiconductor device

Hidetoshi Morokuma, Akiyuki Sugiyama, Yasutaka Toyoda, Wataru Nagatomo, Takumichi Sutani, Ryoichi Matsuoka

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.602066

KEYWORDS: Scanning electron microscopy, Optical proximity correction, Semiconducting wafers, Image processing, Computer aided design, Edge detection, Image segmentation, Semiconductors, Metrology, Wafer testing

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Proceedings Article | 2 June 2003 Paper

New method for the quantitative evaluation of wafer pattern shape based on CAD data

Ryoichi Matsuoka, Masanori Takahashi, Atsushi Uemoto

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483688

KEYWORDS: Computer aided design, Scanning electron microscopy, Lithography, Semiconducting wafers, Semiconductors, Manufacturing, Optical proximity correction, Printing, Solid modeling, Software development

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Proceedings Article | 2 June 2003 Paper

Pattern shape comparison methods using SEM image

Takahiro Ikeda, Toshiya Kotani, Takashi Sato, Kusuo Ueno, Ryoichi Matsuoka

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.482831

KEYWORDS: Computer aided design, Scanning electron microscopy, Semiconducting wafers, Photomasks, Data acquisition, Lithography, Image filtering, Inspection, Data modeling, Algorithm development

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Showing 5 of 15 publications

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