This paper presents a study on a new method to create exposure profiles that are optimized for selected die areas where patterning is critical. This new “region of interest leveling (L-ROI)” method caters for trends in the memory market, where intra-die topography with height steps between for instance cell and periphery areas is commonly observed for several 3D-NAND and DRAM device layers. The method takes advantage of the presence of (periphery) die areas where for some device layers patterning is less important than for other, more critical die areas, like the cell area in 3D-NAND. The L-ROI exposure profiles are insensitive to intra-die topography and to variation of the intra-die topography. They result in tighter focus uniformity (FU) in regions of interest, and thus in tighter CDU as well, than conventional exposures at the cost of an accepted performance degradation in other, non-care areas. Results of a study on a VNAND channel hole layer are presented, including focus performance simulation results and CDU measurement results from in-resist verification of L-ROI functionality on an immersion lithography scanner. The latter show a 31.7% CDU improvement with respect to conventional exposure mode.
The next generation technology and emerging memory devices require gradually tighter lithographic focus control on imaging critical layers. Especially in case of BEOL process, big PDO (Process Dependent Offset) from large intra-field topography steps affects the process margin directly. There are couple of scanner options to reduce PDO, such as AGILE which provides several benefits. However, for certain use cases the AGILE sensor may not be the optimal solution.
In this paper, we introduce the concept and development background of iFPC (intra-field Finger Print Correction). iFPC is a scanner option that removes the generic 3D fingerprint seen in the leveling data so that both process dependency and actual wafer topography are not followed during wafer exposure.
In addition, we compare the degree of process margin improvement when applying iFPC compared to that of AGILE on a critical layer. The achieved results demonstrate that by applying iFPC it is possible to gain an additional 15~20nm DoF. In other words, on this use case our feasibility suggests that by removing the generic 3D fingerprint seen in the leveling data, it is possible to achieve a better focus performance than when trying to follow the topography during scanning.
In conclusion, we found another good way to improve the process margin through this comparative experiment. Therefore, our next step will be to setup the methodology to select the use cases where iFPC is the optimal solution.
Advancement of the next generation technology nodes and emerging memory devices demand tighter lithographic focus control. Although the leveling performance of the latest-generation scanners is state of the art, challenges remain at the wafer edge due to large process variations. There are several customer configurable leveling control options available in ASML scanners, some of which are application specific in their scope of leveling improvement. In this paper, we assess the usability of leveling non-correctable error models to identify yield limiting edge dies. We introduce a novel dies-inspec based holistic methodology for leveling optimization to guide tool users in selecting an optimal configuration of leveling options. Significant focus gain, and consequently yield gain, can be achieved with this integrated approach. The Samsung site in Hwaseong observed an improved edge focus performance in a production of a mid-end memory product layer running on an ASML NXT 1960 system. 50% improvement in focus and a 1.5%p gain in edge yield were measured with the optimized configurations.
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