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In this paper, we introduce the concept and development background of iFPC (intra-field Finger Print Correction). iFPC is a scanner option that removes the generic 3D fingerprint seen in the leveling data so that both process dependency and actual wafer topography are not followed during wafer exposure.
In addition, we compare the degree of process margin improvement when applying iFPC compared to that of AGILE on a critical layer. The achieved results demonstrate that by applying iFPC it is possible to gain an additional 15~20nm DoF. In other words, on this use case our feasibility suggests that by removing the generic 3D fingerprint seen in the leveling data, it is possible to achieve a better focus performance than when trying to follow the topography during scanning.
In conclusion, we found another good way to improve the process margin through this comparative experiment. Therefore, our next step will be to setup the methodology to select the use cases where iFPC is the optimal solution.
Intra-lot wafer by wafer overlay control using integrated and standalone metrology combined sampling
In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer’s behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.
In general the COG at the edge of the slit is often worse than in the center part of the slit. Recently, ASML has released the NXT:1980Di that is equipped with an enhanced illuminator to improve pupil COG variation across the slit. In this paper we explore the performance of this scanner system and show that the AIT variation across the slit is also reduced significantly.
In this paper, we present the insight for the wafer-based overlay correction with optimal measurement resource which is suitable for mass production. The experiment which is the wafer-based overlay correction by several statistical analyses carried out for 2X nm node DRAM. Among them, linear regression is a strong candidate for wafer-based overlay control, which improved up to 0.8 nm of maximum overlay.
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