Ms. Yifan Zhang Profile

Yifan Zhang

at Cadence Design Systems Inc

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Publications (11)

Proceedings Article | 30 March 2017 Paper

Process weakness assessment by profiling all incoming design components

Linda Zhuang, MengFeng Cai, Annie Zhu, Yifan Zhang, Jason Sweis, Ya-Chieh Lai

Proceedings Volume 10148, 1014819 (2017) https://doi.org/10.1117/12.2260311

KEYWORDS: Profiling, Molybdenum, Data processing, Information operations, Manufacturing, Photoacoustic tomography, Excel, Semiconductor manufacturing, Roads, Plutonium

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Proceedings Article | 30 March 2017 Presentation + Paper

Transforming information from silicon testing and design characterization into numerical data sets for yield learning

Thomas Yang, Yang Shen, Yifan Zhang, Jason Sweis, Ya-Chieh Lai

Proceedings Volume 10148, 101480W (2017) https://doi.org/10.1117/12.2259950

KEYWORDS: Failure analysis, Diagnostics, Silicon, Semiconducting wafers, Defect detection, Process engineering, Diagnostic tests, Product engineering, Data processing, Yield improvement, Electrical breakdown, Signal detection

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Proceedings Article | 30 March 2017 Paper

Using design differentiating methods to find suspect design patterns which cause failure

Yang Shen, Thomas Yang, Yifan Zhang, Jason Sweis, Ya-Chieh Lai

Proceedings Volume 10148, 101481C (2017) https://doi.org/10.1117/12.2259947

KEYWORDS: Failure analysis, Diagnostic tests, Diagnostics, Product engineering, Semiconducting wafers, Electrical breakdown, Defect detection, Structural design, Manufacturing, Optical proximity correction

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Proceedings Article | 30 March 2017 Paper

Electrical failure debug using interlayer profiling method

Thomas Yang, Yang Shen, Yifan Zhang, Jason Sweis, Ya-Chieh Lai

Proceedings Volume 10148, 101481D (2017) https://doi.org/10.1117/12.2259944

KEYWORDS: Electrical breakdown, Profiling, Failure analysis, Structural design, Manufacturing, Inspection, Multilayers, Data analysis, Data modeling, Measurement devices, Statistical analysis

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Proceedings Article | 30 March 2017 Paper

Pattern database applications from design to manufacturing

Linda Zhuang, Annie Zhu, Yifan Zhang, Jason Sweis, Ya-Chieh Lai

Proceedings Volume 10148, 101481F (2017) https://doi.org/10.1117/12.2259934

KEYWORDS: Databases, Manufacturing, Design for manufacturability, Semiconductor manufacturing, Roads, Plutonium, New and emerging technologies, Data analysis, Manufacturing equipment, Control systems, Optical proximity correction, Inspection, Product engineering, Statistical analysis, Semiconducting wafers, Failure analysis, Structural design

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Proceedings Article | 28 March 2017 Paper

A pattern-based design analysis method by using inline inspection data more efficiently

Linda Zhuang, Annie Zhu, Yifan Zhang, Jason Sweis, Ya-Chieh Lai

Proceedings Volume 10148, 101480X (2017) https://doi.org/10.1117/12.2259936

KEYWORDS: Structural design, Optical proximity correction, Defect inspection, Semiconducting wafers, Image classification, Databases, Data processing, Inspection, Manufacturing, Silicon

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Proceedings Article | 16 March 2016 Paper

Using pattern enumeration to accelerate process development and ramp yield

Linda Zhuang, Jenny Pang, Jessy Xu, Mengfeng Tsai, Amy Wang, Yifan Zhang, Jason Sweis, Ya-Chieh Lai, Hua Ding

Proceedings Volume 9781, 97810A (2016) https://doi.org/10.1117/12.2219129

KEYWORDS: Manufacturing, Structural design, New and emerging technologies, Profiling, Design for manufacturability, Metals, Silicon, Databases, Image classification, Raster graphics, Product engineering

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Proceedings Article | 16 March 2016 Paper

Migrating from older to newer technology nodes and discovering the process weak-points

Linda Zhuang, Jenny Pang, Jessy Xu, MengFeng Tsai, Xue Long Shi, Qing Wei Liu, Ellyn Yang, Yifan Zhang, Jason Sweis, Ya-Chieh Lai, Hua Ding

Proceedings Volume 9781, 97810L (2016) https://doi.org/10.1117/12.2219561

KEYWORDS: New and emerging technologies, Design for manufacturability, Manufacturing, Acquisition tracking and pointing, Structural design, Profiling, Databases, Electronic design automation, Very large scale integration, Image classification, Optical proximity correction

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Proceedings Article | 16 March 2016 Paper

Using pattern analysis methods to do fast detection of manufacturing pattern failures

Evan Zhao, Jessie Wang, Mason Sun, Jeff Wang, Yifan Zhang, Jason Sweis, Ya-Chieh Lai, Hua Ding

Proceedings Volume 9781, 97810Z (2016) https://doi.org/10.1117/12.2219000

KEYWORDS: Manufacturing, Failure analysis, Silicon, Diagnostics, Defect detection, Environmental sensing, Visibility, Product engineering, Design for manufacturability, Semiconducting wafers, Statistical analysis, Logic, Electrical breakdown, Image classification, Tolerancing

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Proceedings Article | 18 March 2015 Paper

Automation for pattern library creation and in-design optimization

Rock Deng, Elain Zou, Sid Hong, Jinyan Wang, Yifan Zhang, Jason Sweis, Ya-Chieh Lai, Hua Ding, Jason Huang

Proceedings Volume 9427, 94270R (2015) https://doi.org/10.1117/12.2087100

KEYWORDS: Manufacturing, Metals, Lithography, Optical lithography, Silicon, Failure analysis, Electroluminescence, Semiconductor manufacturing, Image classification, Library classification systems

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Semiconductor manufacturing technologies are becoming increasingly complex with every passing node. Newer technology nodes are pushing the limits of optical lithography and requiring multiple exposures with exotic material stacks for each critical layer. All of this added complexity usually amounts to further restrictions in what can be designed. Furthermore, the designs must be checked against all these restrictions in verification and sign-off stages. Design rules are intended to capture all the manufacturing limitations such that yield can be maximized for any given design adhering to all the rules. Most manufacturing steps employ some sort of model based simulation which characterizes the behavior of each step. The lithography models play a very big part of the overall yield and design restrictions in patterning. However, lithography models are not practical to run during design creation due to their slow and prohibitive run times. Furthermore, the models are not usually given to foundry customers because of the confidential and sensitive nature of every foundry's processes. The design layout locations where a model flags unacceptable simulated results can be used to define pattern rules which can be shared with customers. With advanced technology nodes we see a large growth of pattern based rules. This is due to the fact that pattern matching is very fast and the rules themselves can be very complex to describe in a standard DRC language. Therefore, the patterns are left as either pattern layout clips or abstracted into pattern-like syntax which a pattern matcher can use directly. The patterns themselves can be multi-layered with "fuzzy" designations such that groups of similar patterns can be found using one description. The pattern matcher is often integrated with a DRC tool such that verification and signoff can be done in one step. The patterns can be layout constructs that are "forbidden", "waived", or simply low-yielding in nature. The patterns can also contain remedies built in so that fixing happens either automatically or in a guided manner. Building a comprehensive library of patterns is a very difficult task especially when a new technology node is being developed or the process keeps changing. The main dilemma is not having enough representative layouts to use for model simulation where pattern locations can be marked and extracted. This paper will present an automatic pattern library creation flow by using a few known yield detractor patterns to systematically expand the pattern library and generate optimized patterns. We will also look at the specific fixing hints in terms of edge movements, additive, or subtractive changes needed during optimization. Optimization will be shown for both the digital physical implementation and custom design methods.

Proceedings Article | 18 March 2015 Paper

Layout dependent effects analysis on 28nm process

Helen Li, Mealie Zhang, Waisum Wong, Huiyuan Song, Wei Xu, Philippe Hurat, Hua Ding, Yifan Zhang, Michel Cote, Jason Huang, Ya-ch Lai

Proceedings Volume 9427, 94270F (2015) https://doi.org/10.1117/12.2087443

KEYWORDS: Device simulation, Analog electronics, Diffusion, Tolerancing, Manufacturing, Transistors, Semiconductor manufacturing, Roads, Physical phenomena, Design for manufacturability

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Showing 5 of 11 publications

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