In this paper, we provide some data on the actual scaling of OPC runtime that we have experienced at AMD. We review
the expected OPC requirements down to the 16 nm node and develop a model to predict the total CPU requirements to
process a single chip design. We will also review the scalability of "hardware acceleration" under a variety of scenarios.
Reticle cost and cycle time to deliver new circuit designs to a wafer fab remain key focus areas for advanced
semiconductor manufacturing and new product development. Resolution enhancement techniques like optical proximity
correction as applied to critical layers have increased the burden on mask data preparation and reticle writing steps of the
mask making flow. The growing data volume and complexity of designs must be reduced to a perfect image on a reticle
in the shortest time possible against computer and machine constraints. Continued dependence on 193 nm wavelength
exposure in extremely low k1 lithography exacerbates the underlying trends.
Two important factors come together to drive the economics and performance of the reticle line: the complexity of the
designs and the productivity of e-beam writing tools. The designs, OPC methods, and writing tool capabilities continue
to evolve with each node of technology. The study builds on prior evaluations to look at fundamental pattern complexity
across 90nm, 65nm, and 45nm logic designs using the gate and metal-1 critical layers. The writing tool throughput
testing uses a range of standard patterns to establish shot limited performance as a calibration method for arbitrary
designs.
Node to node design and tool to tool generation comparisons highlight actual step changes in complexity and capability
by introducing new quantitative methods, benchmarking metrics, and testing strategies. The findings are projected into
the future using design complexity and writing tool trends to suggest implications about reticle cost, cycle time, or
possible gaps in technology development.
With each new process technology node chip designs increase in complexity and size, and mask data prep flows require
more compute resources to maintain the desired turn around time (TAT) at a low cost. Securing highly scalable
processing for each element of the flow - geometry processing, resolution enhancements and optical process correction,
verification and fracture - has been the focal point so far. The utilization for different flow elements depends on the
operation, the data hierarchy and the device type. This paper introduces a dynamic utilization driven compute resource
control system applied to large scale parallel computation environment. The paper will analyze performance metrics
TAT and throughput for a production system and discuss trade-offs of different parallelization approaches in data
processing regarding interaction with dynamic resource control. The study focuses on 65nm and 45nm designs.
As tolerance requirements for the lithography process continue to shrink, the complexity of the optical proximity
correction is growing. Smaller correction grids, smaller fragment lengths and the introduction of pixel-based simulation
lead to highly fragmented data fueling the trend of larger file sizes as well as increasing the writing times of the vector
shaped beam systems commonly used for making advanced photomasks. This paper will introduce an approach of
layout modifications to simplify the data considering both fracturing and mask writing constraints in order to make it
more suitable for these processes. The trade-offs between these simplifications and OPC accuracy will be investigated.
A data processing methodology that allows preserving the OPC accuracy and modifications all the way to the mask
manufacturing will also be described. This study focuses on 65nm and 45nm designs.
Mask data file sizes are increasing as we move from technology generation to generation. The historical 30% linear
shrink every 2-3 years that has been called Moore's Law, has driven a doubling of the transistor budget and hence feature
count. The transition from steppers to step-and-scan tools has increased the area of the mask that needs to be patterned.
At the 130nm node and below, Optical Proximity Correction (OPC) has become prevalent, and the edge fragmentation
required to implement OPC leads to an increase in the number of polygons required to define the layout. Furthermore,
Resolution Enhancement Techniques (RETs) such as Sub-Resolution Assist Features (SRAFs) or tri-tone Phase Shift
Masks (PSM) require additional features to be defined on the mask which do not resolve on the wafer, further increasing
masks volumes. In this paper we review historical data on mask file sizes for microprocessor, DRAM and Flash memory
designs. We consider the consequences of this increase in file size on Mask Data Prep (MDP) activities, both within the
Integrated Device Manufacturer (IDM) and Mask Shop, namely: computer resources, storage and networks (for file
transfer). The impact of larger file sizes on mask writing times is also reviewed. Finally we consider, based on the trends
that have been observed over the last 5 technology nodes, what will be required to maintain reasonable MDP and mask
manufacturing cycle times.
Mask data file sizes are increasing as we move from technology generation to generation. The historical 30% linear shrink every 2-3 years that has been called Moore's Law, has driven a doubling of the transistor budget and hence feature count. The transition from steppers to step-and-scan tools has increased the area of the mask that needs to be patterned. At the 130nm node and below, Optical Proximity Correction (OPC) has become prevalent, and the edge fragmentation required to implement OPC leads to an increase in the number of polygons required to define the layout. Furthermore, Resolution Enhancement Techniques (RETs) such as Sub-Resolution Assist Features (SRAFs) or tri-tone Phase Shift Masks (PSM) require additional features to be defined on the mask which do not resolve on the wafer, further increasing masks volumes. In this paper we review historical data on mask file sizes for microprocessor designs. We consider the consequences of this increase in file size on Mask Data Prep (MDP) activities, both within the Integrated Device Manufacturer (IDM) and Mask Shop, namely: computer resources, storage and networks (for file transfer). The impact of larger file sizes on mask writing times is also reviewed. Finally we consider, based on the trends that have been observed over the last 5 technology nodes, what will be required to maintain reasonable MDP and mask manufacturing cycle times.
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