Mr. Shinyoung Kim Profile

Shinyoung Kim

at SK Hynix Inc

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Publications (5)

Proceedings Article | 22 February 2021 Poster + Paper

Enhancing model accuracy and calibration efficiency with image-based pattern selection using machine learning techniques

Ren-Cheng Sun, Dae-Kwon Kang, Chester Jia, Meng Liu, De-Bao Shao, Young-Seok Kim, Jangho Shin, Mark Simmons, Qian Zhao, Mu Feng, Yiqiong Zhao, Shibing Wang, Sungho Kim, Sungwoo Ko, Shinyoung Kim, Jaeseung Choi, Chanha Park

Proceedings Volume 11613, 116130Y (2021) https://doi.org/10.1117/12.2584692

KEYWORDS: Calibration, Machine learning, Signal processing, Physics, Optical proximity correction, Metrology, Lithography, Computational lithography

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Proceedings Article | 24 March 2016 Paper

OPC optimization techniques for enabling the reduction of mismatch between overlay metrology and the device pattern cell

Shinyoung Kim, Chanha Park, Jinhyuck Jun, Jaehee Hwang, Hyunjo Yang, Nang-Lyeom Oh, Sean Park, Chris Park, Kyu-Tae Sun, Youping Zhang, Paul Tuffy

Proceedings Volume 9778, 97781S (2016) https://doi.org/10.1117/12.2219467

KEYWORDS: Overlay metrology, Optical proximity correction, Diffraction, Critical dimension metrology, Metrology, Scanning electron microscopy, Electron microscopes, Optical lithography, Error analysis, Target detection

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Proceedings Article | 24 March 2016 Paper

Enhacement of intrafield overlay using a design based metrology system

Gyoyeon Jo, Sunkeun Ji, Shinyoung Kim, Hyunwoo Kang, Minwoo Park, Sangwoo Kim, Jungchan Kim, Chanha Park, Hyunjo Yang, Kotaro Maruyama, Byungjun Park

Proceedings Volume 9778, 97781J (2016) https://doi.org/10.1117/12.2218937

KEYWORDS: Overlay metrology, Metrology, Optical testing, Defect inspection, Inspection, Defect detection, Control systems, Semiconductors, Databases, Distortion, Chemical mechanical planarization, Etching

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Proceedings Article | 28 March 2014 Paper

Layout optimization of DRAM cells using rigorous simulation model for NTD

Jinhyuck Jeon, Shinyoung Kim, Chanha Park, Hyunjo Yang, Donggyu Yim, Bernd Kuechler, Rainer Zimmermann, Thomas Muelders, Ulrich Klostermann, Thomas Schmoeller, Mun-hoe Do, Jung-Hoe Choi

Proceedings Volume 9053, 90530J (2014) https://doi.org/10.1117/12.2046541

KEYWORDS: Photomasks, Optical proximity correction, SRAF, Printing, Semiconducting wafers, 3D modeling, Calibration, Optimization (mathematics), Source mask optimization, Manufacturing

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DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array. Resolution Enhancement Techniques (RET) are used to optimize the periodic pattern process performance. Computational Lithography such as source mask optimization (SMO) to find the optimal off axis illumination and optical proximity correction (OPC) combined with model based SRAF placement are applied to print patterns on target. For 20nm Memory Cell optimization we see challenges that demand additional tool competence for layout optimization. The first challenge is a memory core pattern of brick-wall type with a k1 of 0.28, so it allows only two spectral beams to interfere. We will show how to analytically derive the only valid geometrically limited source. Another consequence of two-beam interference limitation is a ”super stable” core pattern, with the advantage of high depth of focus (DoF) but also low sensitivity to proximity corrections or changes of contact aspect ratio. This makes an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from the very stable regime of periodic patterns to non-periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Above challenge makes the layout correction to a complex optimization task demanding a layout optimization that finds a solution with optimal process stability taking into account DoF, exposure dose latitude (EL), mask error enhancement factor (MEEF) and mask manufacturability constraints. This can only be achieved by simultaneously considering all criteria while placing and sizing SRAFs and main mask features. The second challenge is the use of a negative tone development (NTD) type resist, which has a strong resist effect and is difficult to characterize experimentally due to negative resist profile taper angles that perturb CD at bottom characterization by scanning electron microscope (SEM) measurements. High resist impact and difficult model data acquisition demand for a simulation model that hat is capable of extrapolating reliably beyond its calibration dataset. We use rigorous simulation models to provide that predictive performance. We have discussed the need of a rigorous mask optimization process for DRAM contact cell layout yielding mask layouts that are optimal in process performance, mask manufacturability and accuracy. In this paper, we have shown the step by step process from analytical illumination source derivation, a NTD and application tailored model calibration to layout optimization such as OPC and SRAF placement. Finally the work has been verified with simulation and experimental results on wafer.

Proceedings Article | 29 March 2013 Paper

Process window analysis of algorithmic assist feature placement options at the 2X nm node DRAM

Jinhyuck Jeon, Shinyoung Kim, Jookyoung Song, Chanha Park, Hyunjo Yang, Donggyu Yim, Brian Ward, Yunqiang Zhang, Kevin Hooker, Munhoe Do, Jung-Hoe Choi, Stephen Jang

Proceedings Volume 8684, 86840H (2013) https://doi.org/10.1117/12.2011450

KEYWORDS: SRAF, Atrial fibrillation, Critical dimension metrology, Optical proximity correction, Semiconducting wafers, Photomasks, Model-based design, Manufacturing, Printing, Inspection

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As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits; subresolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. AF placement algorithms can be categorized broadly as either rule-based (RB), model-based (MB). However, combining these different algorithms into new integrated solutions may enable a more optimal overall solution. RBAF is the baseline AF placement method for many previous technology nodes. Although RBAF algorithm complexity limits its use with very extreme illumination, RBAF is still a powerful option in certain scenarios. One example is for repeating patterns in memory arrays. RBAF algorithms can be finely optimized and verified experimentally without the building of complex models. RBAF also guarantees AF placement consistency based only on the very local geometric environment, which is important in applications where consistent signal propagation is of critical importance. MBAF algorithms deliver the ability to reliably place assist features for enhanced process window control across a wide variety of layout feature configurations and aggressive illumination sources. These methods optimize sophisticated AF placement to improve main feature PW but without performing full main feature OPC. The flexibility of MBAF allows for efficient investigations of future technology nodes as the number of interactions between local layout features increases beyond what RBAF algorithms can effectively support Based on hybrid approach algorithms combining features of the different algorithms using both RBAF and MBAF methods, the generation and placement of SRAF can be a good alternative. Combining of two kinds of SRAF placement options might result in relatively improved process window compared to an independent approach since two methods are capable of supplement each other with a complementary advantages. In this paper we evaluate the impact of SRAF configuration to pattern profile as well as CD margin window and manufacturing applications of MBAF and Hybrid approach algorithms compared to the current OPC without AF. As a conclusion, we suggest methodology to set up optimum SRAF configuration using these AF methods with regard to process window.

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