Dr. Vinayan C. Menon Profile

Dr. Vinayan C. Menon

at GLOBALFOUNDRIES Inc

SPIE Involvement:

Author

Publications (8)

Proceedings Article | 31 March 2014 Paper

Characterization and mitigation of overlay error on silicon wafers with nonuniform stress

T. Brunner, V. Menon, C. Wong, N. Felix, M. Pike, O. Gluschenkov, M. Belyansky, P. Vukkadala, S. Veeraraghavan, S. Klein, C. H. Hoo, J. Sinha

Proceedings Volume 9052, 90520U (2014) https://doi.org/10.1117/12.2045715

KEYWORDS: Semiconducting wafers, Overlay metrology, Electronic support measures, Distortion, Optical alignment, Metrology, Photomasks, Lithography, Silicon, Laser range finders

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SPIE Journal Paper | 25 October 2013 Open Access

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Timothy Brunner, Vinayan Menon, Cheuk Wong, Oleg Gluschenkov, Michael Belyansky, Nelson Felix, Christopher Ausschnitt, Pradeep Vukkadala, Sathish Veeraraghavan, Jaydeep Sinha

JM3, Vol. 12, Issue 04, 043002, (October 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.4.043002

KEYWORDS: Semiconducting wafers, Electronic support measures, Overlay metrology, Optical alignment, Silicon, Photomasks, Lithography, Laser range finders, Scanners, Metrology

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Proceedings Article | 4 April 2012 Paper

High-order wafer alignment in manufacturing

Michael Pike, Nelson Felix, Vinayan Menon, Christopher Ausschnitt, Timothy Wiltshire, Sheldon Meyers, Won Kim, Blandine Minghetti

Proceedings Volume 8324, 832408 (2012) https://doi.org/10.1117/12.916483

KEYWORDS: Optical alignment, Semiconducting wafers, Overlay metrology, Scanners, Manufacturing, Control systems, Semiconductor manufacturing, Data modeling, Process control, Metrology

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Proceedings Article | 20 April 2011 Paper

Overlay improvement roadmap: strategies for scanner control and product disposition for 5-nm overlay

Nelson Felix, Allen Gabor, Vinayan Menon, Peter Longo, Scott Halle, Chiew-seng Koay, Matthew Colburn

Proceedings Volume 7971, 79711D (2011) https://doi.org/10.1117/12.879532

KEYWORDS: Overlay metrology, Scanners, Semiconducting wafers, Reticles, Metrology, Optical alignment, Control systems, Photomasks, Image processing, Error analysis

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To keep pace with the overall dimensional shrink in the industry, overlay capability must also shrink proportionally. Unsurprisingly, overlay capability < 10 nm is already required for currently nodes in development, and the need for multi-patterned levels has accelerated the overlay roadmap requirements to the order of 5 nm. To achieve this, many improvements need to be implemented in all aspects of overlay measurement, control, and disposition. Given this difficult task, even improvements involving fractions of a nanometer need to be considered. These contributors can be divided into 5 categories: scanner, process, reticle, metrology, and APC. In terms of overlay metrology, the purpose is two-fold: To measure what the actual overlay error is on wafer, and to provide appropriate APC feedback to reduce overlay error for future incoming hardware. We show that with optimized field selection plan, as well as appropriate within-field sampling, both objectives can be met. For metrology field selection, an optimization algorithm has been employed to proportionately sample fields of different scan direction, as well as proportional spatial placement. In addition, intrafield sampling has been chosen to accurately represent overlay inside each field, rather than just at field corners. Regardless, the industry-wide use of multi-exposure patterning schemes has pushed scanner overlay capabilities to their limits. However, it is now clear that scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieving desired performance. In addition, process (non-scanner) contributions to on-product overlay error need to be aggressively tackled, though we show that there also opportunities available in active scanner alignment schemes, where appropriate scanner alignment metrology and correction can reduce residuals on product. In tandem, all these elements need to be in place to achieve the necessary overlay roadmap capability for current development efforts.

Proceedings Article | 7 March 2008 Paper

Determining DOF requirements needed to meet technology process assumptions

Allen Gabor, Andrew Brendler, Bernhard Liegl, Colin Brodsky, Gerhard Lembach, Scott Mansfield, Shailendra Mishra, Timothy Brunner, Timothy Wiltshire, Vinayan Menon, Wai-kin Li

Proceedings Volume 6924, 69241L (2008) https://doi.org/10.1117/12.773070

KEYWORDS: Critical dimension metrology, Tolerancing, Lithography, Photomasks, Scanners, Semiconducting wafers, Electroluminescence, Optical lithography, Error analysis, Reactive ion etching

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Proceedings Article | 24 March 2006 Paper

Optimization of an integrated and automated macro inspection system for the utilization of wafer color variation detection in a photolithography cluster

Stephen Lickteig, Thomas Forstner, Anthony Barnett, David Dixon, Vinayan Menon, Robert Isaacson, Matthew Nicholls, Yonqiang Liu, Pinar Kinikoglu

Proceedings Volume 6152, 61523B (2006) https://doi.org/10.1117/12.655706

KEYWORDS: Semiconducting wafers, Inspection, Optical lithography, Beam splitters, Diffusers, Defect inspection, Cameras, Light sources, Light, Manufacturing

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Proceedings Article | 24 March 2006 Paper

Product and tool control using integrated auto-macro defect inspection in the photolithography cluster

Vinayan Menon, Robert Isaacson, Matthew Nicholls, Stephen Lickteig, Thomas Forstner, Anthony Barnett, James Mulhall

Proceedings Volume 6152, 61521R (2006) https://doi.org/10.1117/12.656394

KEYWORDS: Semiconducting wafers, Inspection, Optical lithography, Defect inspection, Manufacturing, Defect detection, Metrology, Wafer inspection, Control systems, Optical alignment

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This paper discusses the controls benefit accomplished on both product wafers and process tools at IBM's 300mm wafer manufacturing line by using integrated auto-macro defect inspection in all the photolithography tool clusters for after-develop-inspection (ADI). Inspection is supported on all production wafers (with possibility to sample wafers if desired). To get to this level of control the overall 'ADI process' in the line had to be first rendered manufacturable. Therefore, significant effort had to be focused towards decreasing false fails and nuisance holds. As a result, over the last year inspection software related false fails were reduced 3X, hardware related PC communication fails were decreased 5X, and fab automation related nuisance wafer holds were reduced 12X. Fail rate has been sustainable at 6% (± 2%) for over two quarters. At this point only 20% of the fail rate is false and is mostly attributable to hardware related wafer alignment issues during inspection. By decreasing false fails and hold rates, sensitivity and effectiveness in the line towards correctly reacting to real fail signals significantly improved. Product wafers with real fails are now consistently reacted to real-time in the line leading to rework and elimination of photo sector generated macro defects. Contribution of this integrated metrology system to fab rework rate in eliminating yield impacting macro defects from product wafers, as well as examples of captured defects that have identified several process tool problems are also presented. Majority of rework contributors are defects generated from intermittent photo process tool issues that randomly occur and disappear (versus systematic process tool issues that typically end up being flagged within two consecutive failed lots). Typically 0.5 to 1% of the ADI inspected wafers get reworked for macro defectivity translating to a significant number of wafers - thus justifying ADI return-on- investment. Note that real fails as a result of defectivity propagation from prior photolevels - estimated at 15% of the fail rate, do not get reworked. Additionally, real fails determined to be non-reworkable as a result of defectivity from the current photolevel - estimated at 50% of the fail rate, also do not get reworked. Further, by analyzing real fails for intra/inter wafer signatures systematic process tool issues are being consistently flagged on the line. Overall, ADI at IBM's 300mm wafer fab has evolved into a real-time wafer level go/no-go control for both product and process tools.

Proceedings Article | 10 May 2005 Paper

Implementation of integrated auto macro-defect inspection in the photolithography tool cluster

Richard Lewis, Vinayan Menon, Vandana Vishnu

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.599950

KEYWORDS: Inspection, Semiconducting wafers, Manufacturing, System integration, Defect inspection, Optical lithography, Defect detection, Control systems, Wafer inspection, Telecommunications

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Integrated Auto Macro Defect Inspection was implemented onto all photolithography clusters at IBM’s 300mm wafer manufacturing line. Inspection is performed post photoresist develop step and has resulted in achieving 100% wafer inspection while minimizing tool downtime to less than 5%. This paper discusses the challenges encountered towards making the inspection process manufacturable. The challenges started as tool integration issues during implementation, but have evolved to include hardware and software issues as well. The tool integration issues encountered at the outset pertained to the physical installation of a macro metrology tool into the photolithography tool cluster. Subsequently, the hardware challenges included ensuring that the macro inspection, recipe management, and disposition systems were designed properly in order to effectively receive, send, and store the inspection data. Software challenges, on the other hand, are very similar to those encountered with the automated macro defect inspection standalone tools. With the existing software providing a high degree of defect detection capability the challenge has been more towards decreasing the high number of false fails while ensuring that the true fails do not end up passing inspection. False fails significantly impact manufacturing throughput of the photolithography sector. Ongoing software improvements in response to these false fails have resulted in improving inspection accuracy. False fails are further being addressed by moving towards automated recipe creation (utilizing the scanner/stepper file shot map offset parameters). Heightened sensitivity of non-optimized recipe parameters, also lead to trivial defect fails that are not necessarily reworked. This significantly impacts cycle time while causing tool downtime and thus needs to be avoided. On the other hand preventing true fails from passing inspection involves ensuring that the recipe parameters are adequately sensitized. To further improve automated macro defect inspection several hardware and software improvements have also been pursued. Software improvements include accurately grouping the detected defects and performing automated defect classification into pre-taught categories. Hardware related improvements include improving defect coordinate repeatability and integrating a "smart" system that will provide real-time feedback, thus resulting in automated tool shut down and product rework when necessary. This paper will also discuss the importance of defect detection capability, defect classification, and KLARF file conversion in implementing automated disposition.

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