KEYWORDS: Calibration, Electron beam lithography, Photomasks, Electron beams, Data corrections, Data modeling, Physics, Systems modeling, Monte Carlo methods, Human-machine interfaces
The main source of placement error in maskmaking using electron beam is charging. DISPLACE software
provides a method to correct placement errors for any layout, based on a physical model. The charge of a
photomask and multiple discharge mechanisms are simulated to find the charge distribution over the mask.
The beam deflection is calculated for each location on the mask, creating data for the placement correction.
The software considers the mask layout, EBL system setup, resist, and writing order, as well as other factors
such as fogging and proximity effects correction. The output of the software is the data for placement correction.
Unknown physical parameters such as fogging can be found from calibration experiments. A test layout on a
single calibration mask was used to calibrate physical parameters used in the correction model. The extracted
model parameters were used to verify the correction. As an ultimate test for the correction, a sophisticated
layout was used for verification that was very different from the calibration mask. The placement correction
results were predicted by DISPLACE, and the mask was fabricated and measured. A good correlation of the
measured and predicted values of the correction all over the mask with the complex pattern confirmed the high
accuracy of the charging placement error correction.
KEYWORDS: Calibration, Electron beam lithography, Photomasks, Electrons, Data corrections, Electron beams, Physics, Monte Carlo methods, Systems modeling, Distortion
In maskmaking, the main source of error contributing to placement error is charging. DISPLACE software corrects the placement error for any layout, based on a physical model. The charge of a photomask and multiple discharge mechanisms are simulated to find the charge distribution over the mask. The beam deflection is calculated for each location on the mask, creating data for the placement correction. The software considers the mask layout, EBL system setup, resist, and writing order, as well as other factors such as fogging and proximity effects correction. The output of the software is the data for placement correction. One important step is the calibration of physical model. A test layout on a single calibration mask was used for calibration. The extracted model parameters were used to verify the correction. As an ultimate test for the correction, a sophisticated layout was used for the verification that was very different from the calibration mask. The placement correction results were predicted by DISPLACE. A good correlation of the measured and predicted values of the correction confirmed the high accuracy of the charging placement error correction.
VSB mask writers, which create patterns using a combination of rectangles and 45 degree triangles, are ill-suited to non-
Manhattan geometries. This issue is particularly acute for layouts which contain a large fraction of curvilinear “offangle”
patterns such as photonic or DRAM designs. Unable to faithfully reproduce the “off-angle” structures, traditional
VSB mask writers approximate the desired design using abutted rectangular shots or small shapes to smooth out line
edge roughness. Fidelity to the original pattern comes at a cost of increased shot count and reduced throughput.
Aselta has developed a novel fracture algorithm to dramatically reduce the shot count of such designs. Using a traditional
VSB pattern generator, the new algorithm provides significant shot count reduction. When combined with a modified
JBX-3200MV VSB, the shot count is reduced while maintaining the same level of fidelity. The data preparation software
tool has also the capability of trading off a more accurate level of fidelity with an even more reduced shot count.
The paper will first describe the basic principles of the fracturing algorithm and e-beam writer hardware configuration
then demonstrate the advantage of the method on a variety of patterns.
KEYWORDS: Photomasks, SRAF, Semiconducting wafers, Scanning electron microscopy, Vestigial sideband modulation, Printing, Data modeling, Manufacturing, Error analysis, System on a chip
In writing 22nm logic contacts with 193nm immersion, curvilinear sub-resolution assist features will be desirable on
masks. Curvilinear sub-resolution assist features are good for high volume chips where the wafer volume outweighs
considerations for mask write times. For those chips, even 40 hour write times are tolerated for mask writing. For
lower-volume production of SOC designs, such write times are economically unacceptable. 8 to 12 hours of write times
are feasible for these designs. Previous papers at 2010 Photomask Japan described model-based mask data preparation
(MB-MDP) techniques using circular apertures on production e-beam writers writing curvilinear ideal ILT patterns that
reduced e-beam write-times by nearly a factor of two over conventional approach writing Manhattanized ILT patterns.
This puts the curvilinear assist features within the realm of high-volume production. However, the write times are still
too long for SOC designs. This paper describes a new technique that reduces mask write time further. Resist-exposed
SEM images will be shown, written by JEOL JBX-3200MV. E-beam shot count comparisons for an ideal ILT mask
pattern will be made with the conventional methods, demonstrating a 44% decrease in blanking time. In addition, a
comparison study is shown indicating that an ideal ILT mask pattern that would take 63 hours with conventional
fracturing can be written in about 14 hours using MB-MDP. AIMS projected images demonstrate the pattern fidelity on
the wafer.
As we prepare for 32nm-hp with 193nm immersion, complex and sometimes curvilinear shapes are going to be required
on masks. Contacts and vias will be circular or oval in shape on the wafer, but are still drawn as over-sized squares or
rectangles on masks and in CAD systems. Yet, for packing density of designs, particularly for DRAMs and SRAMs, in
order to optimize for diagonal distances, a circular via shape on the mask is desirable. In addition, a circle has by
definition the minimum perimeter for a given area, improving manufacturing tolerance. This paper demonstrates new
techniques for writing circles of arbitrary diameters on masks efficiently and accurately using a production e-beam mask
writer. Resist-exposed SEM images are shown, demonstrating the practicality of writing circles as mask shapes for
production reticles.
The contact layer for the 22 nm logic node faces many technological hurdles. Even using techniques such as multiple-exposure
patterning and 193 nm immersion, it will be difficult to achieve the depth of focus and CD uniformity required
for 22 nm production. Such difficulties can be mitigated by recent advances in Inverse Lithography Technology (ILT).
For example, circular main features combined with complex curvilinear assist features can provide superior CD
uniformity with the required depth of focus, particularly for isolated contacts. However, such a solution can lead to long
mask write times, because the curvilinear shapes necessitate a higher shot count induced by inefficient data fracturing,
even without considering the circular main features. The current approach is to Manhattanize the curvilinear features
resulting in a nearly equivalent image quality on the wafer; but a further reduction in mask write times could help lower
costs. This paper describes a novel mask-writing method that uses a production e-beam mask writer to write main
features as circles, with curvilinear assist features, while reducing shot count compared to traditional Manhattanized
masks. As a result the new method makes manufacturing of ideal ILT-type masks feasible from a technical as well as
from an economic standpoint. Resist-exposed SEM images are presented that validate the new method.
The metal 1 layer for the 22 nm logic node will require complex "wavy" shapes. These shapes are decorations on main
features and require highly accurate printing in order to meet CD requirements. Despite attempts to reduce mask shot
count by lining up the left-right or top-bottom jogs of the edges, the explosion in the required shot count is considered
inevitable. This paper demonstrates a new mask writing method using model-based mask data preparation (MB-MDP),
on a production e-beam mask writer. MB-MDP is a complementary technology to conventional fracturing. It
incorporates e-beam simulation as an integrated part in order to determine the dose and shape of the overlapping shots to
draw complex mask shapes with less shot count. Specifically, the new method writes these "wavy" metal 1 wires
accurately with a significant reduction in shot count. Resist-exposed SEM images will be shown that validate the mask
simulation results. A shot count comparison will be made with conventional methods.
Lithography technologies promising for the half pitch (HP) 32 nm generation include 193 nm immersion with water,
extreme ultraviolet lithography (EUVL), and nano-imprint lithography (NIL). Among these, 193 nm immersion with
water is considered a mainstream for hp 32 nm device fabrication in terms of performance and device production costs.
Meanwhile, according to the International Technology Roadmap for Semiconductors (ITRS) 2009, the optical masks for
hp 32 nm devices need to meet extremely strict requirements; for example, an image placement accuracy of 3.8 nm (2.7
nm for double patterning), and CD uniformities of 1.5 nm (isolated lines) and 2.4 nm (dense lines).
To meet these accuracy requirements, we have developed JBX-3200MV, a variable shaped beam mask writer featuring
an accelerating voltage of 50 kV and a current density of 70 A/cm2. For this new writer, we developed a new
digital-to-analog converter (DAC) amplifier designed to reduce noises input to electron beam optics components such as
the main and sub positioning deflectors and the beam shaping deflectors. The stage and exposure chambers were
enhanced in rigidity to reduce mechanical noises. The position of the stage is measured by laser devices with a finer
resolution of 0.15 nm, and the measured results are fed back to the beam position. In addition, data transfer speed and
proximity correction speed were improved to handle larger data volumes.
Our exposure test results demonstrate that the new lithography system, installed at the leading-edge mask production
facility, achieved the hp 32 nm mask accuracies required by the ITRS 2009.
KEYWORDS: Photomasks, Data processing, Lithography, Computing systems, Reliability, Data storage, Resolution enhancement technologies, Digital recording, Optical proximity correction, Control systems
To extend the effectiveness of photo lithography, Optical Proximity Effect Correction (OPC) and Resolution
Enhancement Technique (RET) incorporate increasingly complicated process steps, handling large volumes of data.
This poses a challenge for mask making with EB lithography in two areas: data transfer speed and the reliability of
pattern data processed by hardware.
Traditionally, JEOL's variable shaped beam mask writers used single board CPU control to save in buffer memory
pattern data per field on a magnetic disk. We developed a new parallel transfer technique using a dual board CPU to
enhance the data transfer speed to buffer memory. This technique improved the data transfer speed from 40 MB/sec to
80 MB/sec or higher.
To insure the reliability of pattern data processed by hardware, we also devised a way to save in the hard disk the
shot position, size, and dose of patterns processed in the data transfer system. We verified that the system was able to
record in real time 250G shot pattern data (size and positional data of figures to be exposed).
This paper presents an experimental study of resist charging of mask blanks written with a variable shaped electron beam
mask writer. Experiments were performed at a current density of 40 A/cm2 on mask blanks with a chemically amplified
resist. Test patterns were written to examine the magnitude of the pattern shift due to resist charging and the distance
within which the pattern shift is significant. To reduce the pattern shift due to resist charging, furthermore, similar test
patterns were written with a two-pass scanning in which both horizontal and vertical scanning directions are different
between the two passes. With this writing method, the pattern shift was successfully reduced to about half.
This paper presents an experimental study of resist heating effect in mask making with a variable shaped electron beam
mask writer. Experiments were performed at current densities of 40 and 80 A/cm2 on mask blanks with a chemically
amplified resist. At these levels of current density, the critical dimension change due to resist heating effect was obvious.
The critical dimension change was reduced with a checkerwise writing method, in which sub-fields were arranged in
main fields in an alternate fashion so that the average incoming heat per unit area due to beam exposure could be reduced.
The reduction factor was 2 or more.
The composite critical dimension (CD) and registration performance of a photomask is limited partly by systematic constituent mask lithography tool errors. Test masks can be designed specifically to isolate these error sources so they can be measured and characterized independently from other error sources. This methodology allows the creation of a composite CD and registration error budget that can be used to realistically specify mask lithography tool requirements and predict actual performance on masks from these tools.
In this study, we investigate the local CD and Registration errors that occur within a single deflection field on the JEOL JBX-9000MV vector shaped beam (VSB) electron-beam mask lithography system. Test patterns were designed to hold proximity, fogging, and loading effects constant and thereby show the true constituent error of the system. One advantage of using the JBX-9000MV in this study is that the step-and-repeat stage motion makes the position of each feature within the deflection field unambiguous compared to other VSB tools that use continuous stage motion. It is therefore relatively straightforward to characterize and compensate deflection errors.
The authors will present experimental characterization of the constituent errors observed within a single deflection field. In addition, we will show how these errors can be controlled through increased shot settling time, increased deflection calibration, and multi-pass writing.
A 65 nm node mask is required to have total alignment accuracy of 20 nm (3σ) or less for 1st and 2nd layers, including the positional accuracy of each layer. We have developed a new electron beam mask lithography process using “alignment-and-height” marks to minimize the displacement between two layers resulting from additional bowing and contraction on the blank surface after the 1st layer exposure. The new process consists of the following steps: 1. Write “alignment-and-height” marks on the edge of a mask simultaneously with the pattern of the 1st layer. 2. Measure the position and height of “alignment-and-height” marks before writing the 2nd layer. 3. Create a position/height correction map to write the 2nd layer. 4. Write the 2nd layer with reference to the correction map. Basic system attributes, such as beam origin and positional drift of mask blank, are monitored and adjusted throughout the process. We tested the process and achieved an alignment accuracy of 20 nm (3σ) between 1st and 2nd layers regardless of the density of the pattern area ratio, confirming that the process is effective for 65 nm node phase shift mask exposure.
We have developed a high alignment-accuracy electron beam (EB) mask writing processes of phase shift layer using alignment-and-height marks. The new process consists of (1) First layer writing with “alignment-and-height” marks on peripheral area of the mask patterns; (2) Development of resist, Cr etching of the first layer pattern and coating of new resist; (3) Measurement of position, height and rotation of “alignment-and-height” marks with electron beams; (4) Create alignment map, scanning distortion correction map for the second layer writing; (5) Second layer pattern writing
using these correction maps. We performed a set of evaluation test of the processes and confirmed that an overlay alignment accuracy of within 16nm (3 sigma) between first and second layer is attainable, and thus, practically effective for phase shift image writing of 65nm node masks.
A new advanced electron beam lithography system JBX-3030MV has been developed to meet requirements for the production of masks for 100-90nm technology node. The system features a variable shaped beam, 50kV accelerating voltage, a step-and-repeat stage, and incorporates new technologies. These include a high resolution-high current density electron optical system, triangle beam shaping system, higher speed electro static beam deflection system, higher accuracy proximity effect correction system, and glass in glass out material handling system. The writing accuracy of the system has satisfied the specifications required for the production of 100-90nm node reticles with extendibility of 65nm node reticles.
An electron beam mask writing system JBX-9000MV for 150- 180nm technology node masks was developed by JEOL Ltd. and its design concept, technologies introduced and results of initial evaluation were reported in 1998. We have improved this system to cope with the production of masks for 130nm technology node. Some of the new technologies developed for the improvement of writing accuracy, especially CD accuracy, and the results are reported in this paper.
An electron beam mask writing system JBX-9000MV for 150- 190nm technical node masks was improved to cope with the production of masks for 130nm technology node. Some of the new technologies developed for the improvement and their results are reported in this paper.
JEOL has developed an E-Beam lithography system JBX-9000MV with a vector scan and variable shaped beam (VSB) electron optics for the manufacture of 180nm - 150nm devices masks. This system employs 50kV accelerating voltage, low space charge effect column and in-lens deflector system. Beam current density is 10A/cm2, maximum mask size is 230 mm (9'), beam address size is 2 nm. Extended evaluation of the system shows pattern placement accuracy of 30 nm or better, field stitching accuracy of 20 nm or better, critical dimension (CD) accuracy of 20 nm or better.
One of the keys for ULSI lithography at a feature size ranging from 180 nm to 150 nm is a stable supply of ultra high precision reticle masks. To meet this demand, we have developed a new electron beam lithography system for reticle masks which offers an exposure accuracy of 20 to 30 nm. The system features a variable shaped beam, 50 kV accelerating voltage, a step-and-repeat stage, nd incorporates new technologies. These include a high resolution-high current density electron optical system, a per-shot focus and shot time correction unit, a high precision beam measurement system utilizing the fitting function method, a single-stage 20 bit electrostatic beam deflection unit and beam-shot smoothing technology. The system achieves a minimum line width of 100 nm or less, a pattern size uniformity of 16 nm (3 sigma) within a field, a field stitching accuracy of plus or minus 19 nm or smaller, and a pattern placement accuracy of plus or minus 29 nm or smaller, resulting in an exposure speed of 3 to 5 times faster than the existing model.
A new electron beam lithography system for masks needed in production of 1Gbit DRAM devices was developed and evaluated. The system features a variable shaped beam, 50 kV accelerating voltage, and a step and repeat stage, and incorporates new technologies, including a high resolution high current density electron optical system, a per-shot beam correction unit, a high precision beam detection system utilizing the curve fitting method, and a single-stage 20 bit beam deflection unit. The initial evaluation confirmed a minimum line-width of 100nm, a line-width uniformity of 20 nm within a field, a total positional accuracy, including field stitching and in-field positional accuracy of 20 nm and an exposure speed 3 times faster than that of the existing model, JBX-7000MVII. It was thus verified that the new EB system is capable to produce masks needed for next generation devices including 1 Gbit DRAMs.
A new electron beam lithography system for masks needed in production of 1Gbit DRAM devices was developed and evaluated. The system features a variable shaped beam, 50 kV accelerating voltage, and a step and repeat stage, and incorporates new technologies, including a high resolution high current density electron optical system, a per-shot beam correction unit, a high precision beam detection system utilizing the curve fitting method, and a single-stage 20 bit beam deflection unit. The system achieves a minimum linewidth of 200 nm or less, pattern uniformity of 20 nm within field, and a positional accuracy, including field stitching accuracy, of 20nm within a field, resulting in an exposure speed at least 5 times faster than the existing model, the JBX-7000MVII.
Mask accuracies for the newest and next generation devices are very tight. The SIA Roadmap indicates writing accuracies (CD uniformity) of 18 nm and 13 nm for 1-Gbit and 4-Gbit DRAM 4X reticles, respectively. To meet this challenge, a new electron optical column is being developed for an electron beam mask writing system. The column has a beam current density of 20 A/cm2 (50 kV), a beam blurring of 0.06 micrometer at a 16 micrometer2 beam size, and a total aberration of less than 0.05 micrometer at 1 mm deflection length. The key technologies for this column are as follows: (1) Shorter column length and wider beam half-angle for reduction of Coulomb interaction; (2) Per shot focus correction of space charge effect; (3) In-lens, single stage electrostatic beam deflection system with focus and astigmatism correction. In this paper, we report the simulation results of this electron optical column design.
A higher quality electron beam (EB) mask lithography system is now required in an advanced field aimed at 1 Gbit DRAM chips. For this purpose, photomask accuracies of 0.03 micrometers to 0.02 micrometers are needed, for the feasibility of an EB lithography system with these accuracy levels is discussed. The error sources of a commercial EB lithography system with a variable shaped beam system and step and repeat writing strategy are examined. The development plans to minimize these errors are described and early results, specifically the field stitching error, obtained from these developments are shown. The mean stitching error was +/- 0.023 micrometers and the random stitching error was +/- 0.030 micrometers . From the analysis of error budget, it is shown that a field stitching accuracy level of 0.02 micrometers will be attainable after the completion of above-mentioned development plans.
KEYWORDS: Reticles, Distortion, Photomasks, Beam shaping, Data corrections, Data conversion, Lithography, Electron beams, Semiconductors, Electron beam lithography
The semiconductor industry has directed its course toward volume production of 64M DRAMs. Feature sizes of typical 64M DRAM are 0.3 to 0.4 micrometers , and the linewidth and positioning accuracies required for 5X reticle production are both 0.05 micrometers . To respond to these requirements, JEOL has developed an electron beam lithography system for reticle making, JBX-7000MV, which incorporates improved variable shaped beam optics to assure high speed and highly accurate pattern writing. The high accuracy writing was made possible by: (1) reducing the pattern data increment and correction increments by 1/2; (2) applying a field shift writing method; and (3) a new substrate holder insensitive to the weight of a mask. This paper introduces the JBX-7000MV and its capabilities, and discusses the issues required for second generation 64M DRAM reticles. Anticipated improvements expected to be integrated in the JBX-7000MV to meet these requirements are discussed.
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