Nanoimprint lithography has advantages such as good resolution, CD uniformity and LER. However, nanoimprint
lithography involves risks. In particular, defectivity is the most critical issue for nanoimprint lithography. Above all, the
"non-fill defects" dominate such defects for UV nanoimprint.
At the filling process of imprint resist, the capillary force that occurs between an imprint-resist and surface of template
plays an important role. Our experience, suggests there is a relationship between the filling characteristics and pattern
size of template. We also think the resist properties and the environmental conditions such as atmosphere pressure play
important roles in the filling process. This paper explains the filling process dependency on the properties mentioned
above.
We analyzed the filling process using fluid simulation. At first, we assumed several pattern sizes with the same pattern
height. Then, the filling times were estimated for each pattern size with various resist properties and the environmental
conditions. An important attribute of our simulation model is the consideration accorded to the dissolution of gas
between the template and imprint resist.
As a result, the filling time of smaller pattern was found to be shorter than that of larger pattern. The assumed patterns
are space and via on template ranging in size from 22nm width to 1000nm-width. The pattern height is 60nm.
In this paper, we studied characteristics of filling mechanism by using fluid simulation. The relations between CD and
filling time were obtained. We found that the gas dissolution rate is the dominant parameter for filling time.
We have investigated three candidate lithography technologies for 2x nm HP generation and beyond for the
application to LSI, namely, double patterning technology (DPT), EUV lithography (EUVL) and nanoimprint
lithography (NIL). In terms of lithography unit technologies and lithography integration technologies, each technology
has advantages and disadvantages from the viewpoint of difficulty, development resources, extendability, process cost,
and so on. Using a development matrix consisting of development steps and development stages, we clarified the
current development status for each technology. This matrix indicates the items for which technological critical
breakthroughs are necessary to realize LSI production. From this study, we made three lithography development
scenarios for the feasibility stage and the production stage for 2x nm HP generation and beyond.
Nanoimprint lithography is one of the candidates for NGL. Recently, the "S-FIL TM" (Step and Flash Imprint
Lithography) has been developed by MII (Molecular Imprints, Inc.). Accordingly, it is necessary to build next-generation
devices and study unit processes without delay. Because of good resolution, CD uniformity and LER, nanoimprint
lithography is attractive. However, nanoimprint lithography (S-FIL) involves risks. In order to judge whether the S-FIL
is applicable to the study of unit processes and test device fabrication, we had studied the feasibility of S-FIL technology.
As a result of previous work, we obtained the results of basic evaluation and confirmed the applicability of nanoimprint
lithography for unit process study and basic test device fabrication.
However, application of nanoimprint lithography to various test devices requires the template resolution of 22nmHP, OL
accuracy on multilayer resist, and defect density for various patterns. Therefore, in order to judge whether the S-FIL
application is extendable to various test devices, we studied the characteristics of S-FIL.
As a result of this work, we confirmed that the nanoimprint application is extendable to fabrication of various test
devices. And as a result of basic evaluation, improvement of template resolution is confirmed and the value of 22nmHP
is obtained. We confirmed the robustness of the alignment process. The defect density is related in pattern density and
spread time. Thus, reduced DD without throughput loss is required.
KEYWORDS: Monte Carlo methods, Virtual colonoscopy, Silicon, Scattering, Polymethylmethacrylate, Electron beams, Computing systems, Scanning electron microscopy, Lithography, 3D image processing
Using Monte Carlo simulation, we studied voltage contrast (VC) image caused by negative charging. In order to simulate
the VC image, we have developed an electron scattering program based on a consideration of the spatial charge
conduction model. Also we have established a cluster computing system of 60 CPUs to shorten the processing time.
Using a Monte Carlo simulator, we succeeded in obtaining the simulated VC image. Comparison between simulated
images and experimental images reveals that the simulated images are in good agreement with some experimental images.
KEYWORDS: Virtual colonoscopy, Optical alignment, Signal detection, Silicon, Metals, Image analysis, Overlay metrology, Lithography, Distortion, Back end of line
We have developed the EBIS (Electron Beam Integrated System), which is a character projection (CP) type low-energy electron-beam direct writing (LEBDW) system. In this system, the proximity effect due to backscattering electrons is very small under the condition that the energy of primary electron is 5 keV. However, there is a serious problem, in that the signal of the mark buried under a thick insulator couldn't be detected. To overcome this problem, we adopted a mark detection method using Voltage Contrast (VC) image with negative charge on the sample surface.
So far, we have detected the signal of alignment mark buried under 600nm-thick (nmt) tri-layer resist using VC image on EBIS. Then we exposed overlay patterns with alignment using the mark detection with VC image. The mark image is very clear with a sufficiently high contrast. The asymmetry originating from VC is mitigated by means of FB scanning. Using this VC mark detection method, EB drawing was performed with alignment with 600nmt tri-layer resist on Si substrate. Moreover, VC mark detection with 600nmt tri-layer resist on the substrates of back-end-of-line (BEOL) of logic device was performed and the mark images with sufficient contrast were obtained. Although the characteristic distortion of VC image exists, mark detection is possible by using X/Y separate scanning, which consists of X-direction scanning to get an X position and Y-direction scanning to get a Y position in non-charged area.
KEYWORDS: Semiconducting wafers, Electron beam direct write lithography, Control systems, Electron beams, Vestigial sideband modulation, Data conversion, Beam shaping, Photomasks, Optical alignment, Amplifiers
A character projection (CP)-type, low energy, electron beam direct writing (EBDW) system, for quick-turn-around-time and mask-less device fabrications of small production lots featuring a variety of designs has been developed. This system, named the EBIS (Electron Beam Integrated System), can satisfy a set of requirements for EBDWs, including higher throughput and mask-less exposure. A standardized CP aperture method that enables reduction in the number of EB shots without frequent aperture making has been applied as a means for attaining effective CP and mask-less fabrication. This breakthrough was able to be realized only by using low energy EB with the advantage of the free proximity effect. To resolve critical low energy EB issues, a compact EB column, equipped with monolithic deflectors and lenses for restricting beam blur caused by Coulomb interaction, was developed and put to use. Sufficient resolution, corresponding to 100 nm L/S patterns, was attained by using a thin-layered resist process. As the mark detection method, voltage contrast imaging using a micro channel plate was used. This method made it possible to detect buried marks when using low energy EB. The authors are currently verifying the basic performance of this EBIS. This paper outlines and discusses geometrical details and performance data of this system.
KEYWORDS: Scanning electron microscopy, Virtual colonoscopy, System on a chip, Logic devices, Maskless lithography, Lenses, Semiconducting wafers, Inspection, Electron beam direct write lithography, Lithography
In order to realize SoC (System on a Chip) fabrication at low cost with quick-TAT (Turn-Around-Time) we have proposed a maskless lithography (ML2) strategy, a low-energy electron-beam direct writing (LEEBDW) system with a common character projection (CP) aperture. This paper presents a status report on our proof-of-concept (POC) system. We have developed a compact EB column consisting small electrostatic lenses and deflectors. The experimental results for our POC system indicated that the patterns corresponding to 50nm-node logic devices can be obtained with CP exposure at the incident energy of 5 keV. The technique to reduce the raw process time using a SEM function of LEEBDW system is also reported.
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