Introducing NEOGLY™, a novel body-worn QCL-based non-invasive continuous glucose monitoring device (NI-CGM). Developed under ISO 13485 regulation, it shows relevant glycemia predictions based on mid-infrared photoacoustic spectroscopy as well as AI-based algorithms fed by a digital twin that covers the entire detection chain including device modeling and human skin properties.
The integration of new materials in the next generation of optoelectronic devices leads to several challenges. For instance, the etching of indium tin oxide (ITO, In2O3:Sn) faces the issue of the low volatility of In- and Sn-based etch products at room temperature. This is challenging for the etching process itself, but even more problematic when the inductively coupled plasma (ICP) reactor must be cleaned after etching: since the reactor walls are bombarded by low energy ions only, the removal of In- and Sn-based products redeposited on the walls can be very long and laborious. Therefore, we have investigated several plasma chemistries to find the most efficient reactor cleaning process suitable for ITO plasma etching. The results show that after ITO plasma etching the walls are indeed contaminated by indium. At the low temperature at which the reactor walls are regulated, BCl3/Cl2 cleaning plasma is ineffective to remove this deposit while HBr and CH4/Cl2 chemistries provide promising results.
KEYWORDS: Directed self assembly, Lithography, Line width roughness, Nanoimprint lithography, Semiconducting wafers, Etching, Electron beam lithography, System on a chip, Critical dimension metrology, Photoresist processing
In the lithography landscape, EUV technology recovered some credibility recently. However, its large adoption remains uncertain. Meanwhile, 193nm immersion lithography, with multiple-patterning strategies, supports the industry preference for advanced-node developments. In this landscape, lithography alternatives maintain promise for continued R&D. Massively parallel electron-beam and nano-imprint lithography techniques remain highly attractive, as they can provide noteworthy cost-of-ownership benefits. Directed self-assembly lithography shows promising resolution capabilities and appears to be an option to reduce multi-patterning strategies. Even if large amount of efforts are dedicated to overcome the lithography side issues, these solutions introduce also new challenges and opportunities for the integration schemes.
For sub-10nm technologies, the semiconductor industry is facing the limits of conventional lithography to achieve narrow dimensions. DSA (Directed Self-Assembly) of Block Copolymers (BCP) is one of the most promising solutions to reach sub-10nm patterns with a high density. One challenge for DSA integration is the removal of PMMA selectively to PS. In this paper, we propose to study PMMA removal selectively to PS by screening different plasma etch chemistries. These chemistries developed on blanket wafers have been tested on cylindrical and lamellar patterned wafers.
Ar/Cl2/CH4 gas mixture has been investigated for the development of plasma etching process dedicated to the patterning of 3μm-deep InP structures integrated on 200mm SiO2 carrier wafer. The plasma process requirements are: high InP etch rates (>500nm.min-1), high InP/SiO2 selectivity (<40), anisotropic profiles and smooth bottom and sidewalls surfaces. The process development mainly focuses on the impact of the gas ratio and gas flow on the etch rates, selectivity, pattern profile and surface roughness. It is demonstrated that the CH4 flow drives the process performance and that by adjusting it properly, a narrow process window provides acceptable selectivity of 25, anisotropic profiles and smooth surface. The difficulty of the process development using Ar/Cl2/CH4 gas mixture is to combine high InP/SiO2 selectivity and anisotropic profiles since to passivate efficiently the InP sidewalls and prevent from lateral etching, it seems that a SiOC like deposition is needed, which is only possible if the SiO2 wafer is etched.
Density multiplication and contact shrinkage of patterned templates by directed self-assembly (DSA) of block copolymers (BCP) stands out as a promising alternative to overcome the limitations of conventional lithography. The main goal of this paper is to investigate the potential of DSA to address contact and via levels patterning with high resolution by performing either CD shrink or contact multiplication. Different DSA processes are benchmarked based on several success criteria such as: CD control, defectivity (missing holes) as well as placement control. More specifically, the methodology employed to measure DSA contact overlay and the impact of process parameters on placement error control is detailed. Using the 300mm pilot line available in LETI and Arkema’s materials, our approach is based on the graphoepitaxy of PS-b-PMMA block copolymers. Our integration scheme, depicted in figure 1, is based on BCP self-assembly inside organic hard mask guiding patterns obtained using 193i nm lithography. The process is monitored at different steps: the generation of guiding patterns, the directed self-assembly of block copolymers and PMMA removal, and finally the transfer of PS patterns into the metallic under layer by plasma etching. Furthermore, several process flows are investigated, either by tuning different material related parameters such as the block copolymer intrinsic period or the interaction with the guiding pattern surface (sidewall and bottom-side affinity). The final lithographic performances are finely optimized as a function of the self-assembly process parameters such as the film thickness and bake (temperature and time). Finally, DSA performances as a function of guiding patterns density are investigated. Thus, for the best integration approach, defect-free isolated and dense patterns for both contact shrink and multiplication (doubling and more) have been achieved on the same processed wafer. These results show that contact hole shrink and multiplication approach using DSA is well compatible with the conventional integration used for CMOS technology.
In this paper we report on advances in DUV dry photolithography both for etching and implantation of silicon photonic devices. We explain why silicon patterning is a critical building block in silicon photonics and what are the challenges related to that process. Furthermore, it also occurs that some silicon photonic devices need implantation lithographic conditions which are also specific to the technology. For that purpose, we developed a dedicated DUV 193nm implantation lithography to address that need.
Directed Self-Assembly (DSA) of Block Copolymers (BCP) is one of the most promising solutions for sub-10 nm nodes. However, some challenges need to be addressed for a complete adoption of DSA in manufacturing such as achieving DSA-friendly design, low defectivity and accurate pattern placement. In this paper, we propose to discuss the DSA integration flows using graphoepitaxy for contact-hole patterning application. DSA process dependence on guiding pattern density has been studied and solved thanks to a new approach called “DSA planarization”. The capabilities of this new approach have been evaluated in terms of defectivity, Critical Dimension (CD) control and uniformity before and after DSA etching transfer.
We report a 20 nm half-pitch self-aligned double patterning (SADPP) process based on a resist-core approach. Line/space 20/20 nm features in silicon are successfully obtained with CDvariation, LWR and LER of 0.7 nm, 2.4 nm and 2.3 nm respectively. The LWR and LER are characterized at each technological step of the process using a power spectral density fitting method, which allows a spectral analysis of the roughness and the determination of unbiased roughness values. Although the SADP concept generates two asymmetric populations of lines, the final LLWR and LER are similar. We show that this SADP process allows to decrease significantly the LWR and the LER of about 62% and 48% compared to the initial photoresist patterns. This study also demonstrates that SADP is a very powerful concept to decrease CD uniformity and LWR especially in its low-frequency components to reach sub-20 nm node requirements. However, LER low-frequency components are still high and remain a key issue tot address for an optimized integration.
KEYWORDS: Etching, Electron beam lithography, Polymethylmethacrylate, Silicon, Picosecond phenomena, Photomasks, Chemistry, Lithography, System on a chip, Metals
For 11nm and below, several alternatives are still potential candidates to meet the patterning requirements. Spacer patterning, Mask Less Lithography (i.e. Electron beam lithography) and Direct Self Assembly are alternatives under development at CEA-LETI. We have demonstrated the integration of these alternative techniques in front end of line and back end of line levels. Common challenges such as minimum achievable CD, CD control through the integration steps, mask budget and LWR were compared for these techniques.
Directed Self-Assembly (DSA) is today a credible alternative lithographic technology for semiconductor industry [1]. In the coming years, DSA integration could be a standard complementary step with other lithographic techniques (193nm immersion, e-beam, extreme ultraviolet). Its main advantages are a high pattern resolution (down to 10nm), a capability to decrease an initial pattern edge roughness [2], an absorption of pattern guide size variation, no requirement of a high-resolution mask and can use standard fab-equipment (tracks and etch tools). The potential of DSA must next be confirmed viable for high volume manufacturing. Developments are necessary to transfer this technology on 300mm wafers in order to demonstrate semiconductor fab-compatibility [3-7]. The challenges concern especially the stability, both uniformity and defectivity, of the entire process, including tools and Blok Co-Polymer (BCP) materials. To investigate the DSA process stability, a 300mm pilot line with DSA dedicated track (SOKUDO DUO) is used at CEALeti. BCP morphologies with PMMA cylinders in a PS matrix are investigated (about 35nm natural period). BCP selfassembly in unpatterned surface and patterned surface (graphoepitaxy) configurations are considered in this study. Unpatterned configuration will initially be used for process optimization and fix a process of record. Secondly, this process of record will be monitored with a follow-up in order to validate its stability. Steps optimization will be applied to patterned surface configurations (graphoepitaxy) for contact hole patterning application. A process window of contact hole shrink process will be defined. Process stability (CD uniformity and defectivity related to BCP lithography) will be investigated.
This paper reports on the etch challenges to overcome for the implementation of PS-b-PMMA block copolymer’s Directed Self-Assembly (DSA) in CMOS via patterning level. Our process is based on a graphoepitaxy approach, employing an industrial PS-b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology. The process consists in the following steps: a) DSA of block copolymers inside guiding patterns, b) PMMA removal, c) brush layer opening and finally d) PS pattern transfer into typical MEOL or BEOL stacks. All results presented here have been performed on the DSA Leti’s 300mm pilot line. The first etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block. In our process baseline, an acetic acid treatment is carried out to develop PMMA domains. However, this wet development has shown some limitations in terms of resists compatibility and will not be appropriated for lamellar BCPs. That is why we also investigate the possibility to remove PMMA by only dry etching. In this work the potential of a dry PMMA removal by using CO based chemistries is shown and compared to wet development. The advantages and limitations of each approach are reported. The second crucial step is the etching of brush layer (PS-r-PMMA) through a PS mask. We have optimized this step in order to preserve the PS patterns in terms of CD, holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrinking by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching.
Contact hole (CH) patterning by directed-self-assembly (DSA) of polystyrene-b-polymethylmethacrylate (PS-b-PMMA) block copolymers (BCPs) is extensively studied in this paper. Based on statistical analysis performed on 300mm wafers, a process window (PW) for CH shrink is experimentally evaluated in terms of hole open yield and critical dimension (CD) variation after DSA as a function of BCPs of different natural periods and guiding patterns of different dimensions. The PW allowed us to define the suitable BCP molecular weight with the best guiding CD ranges required to achieve a desired DSA hole CD within a specific tolerance. As example, for a DSA hole CD targeted at 19.5 nm with 10% tolerance, circular guiding patterns of 52 nm CD with 20% guiding CD latitude are needed using a 35nm-natural-period BCP. It is also shown that the CH shrink PW is dependent on guiding pattern pitch and on DSA process conditions such as the self-assembly annealing and spin coating conditions. In addition, the study highlights an interesting property of commensurability between guiding pattern dimensions and BCP’s natural period that governs the CH patterning by DSA for both CH shrink and CH doubling configurations. This permits to predict the guiding pattern dimensions needed for CH patterning by DSA using a given BCP of known natural period.
We demonstrate the feasibility of producing advanced silicon photonic devices for future data communication nodes at 40Gbps using CMOS compatible processes in a 300mm wafer fab. Basic building blocks are shown together with various wavelength division multiplexing solutions. All the devices presented are integrated on 220nm SOI or locally grown epitaxial germanium.
The goal of this paper is to investigate the potential of Directed Self-Assembly (DSA) to address
contact via level patterning, by either Critical Dimension (CD) shrink or contact multiplication. Using the
300mm pilot line available in LETI and Arkema materials, our approach is based on the graphoepitaxy of PS-b-
PMMA block copolymers (BCP). The process consists in the following steps: a) the lithography of guiding
patterns, b) the DSA of block copolymers and PMMA removal and finally c) the transfer of PS patterns into the
under-layer by plasma etching.
Several integration schemes using 193nm dry lithography are evaluated: negative tone development
(NTD) resists, a tri-layer approach, frozen resists, etc. The advantages and limitations of each approach are
reported. Furthermore, the impact of the BCP on the final patterns characteristics is investigated by tuning
different parameters such as the molecular weight of the polymeric constituents and the interaction with the
substrate. The optimization of the self-assembly process parameters in terms of film thickness or bake
(temperature and time) is also reported. Finally, the transfer capabilities of the PS nanostructures in bulk silicon
substrate by using plasma-etching are detailed.
These results show that DSA has a high potential to be integrated directly into the conventional CMOS
lithography process in order to achieve high-resolution contact holes. Furthermore, in order to prevent design
restrictions, this approach may be extended to more complex structures with multiple contacts and nonhexagonal
symmetries.
A roadmap extending far beyond the current 22nm CMOS node has been presented several times. [1] This roadmap
includes the use of a highly regular layout style which can be decomposed into "lines and cuts."[2] The "lines" can be
done with existing optical immersion lithography and pitch division with self-aligned spacers.[3] The "cuts" can be done
with either multiple exposures using immersion lithography, or a hybrid solution using either EUV or direct-write ebeam.[
4] The choice for "cuts" will be driven by the availability of cost-effective, manufacturing-ready equipment and
infrastructure.
Optical lithography improvements have enabled scaling far beyond what was expected; for example, soft x-rays (aka
EUV) were in the semiconductor roadmap as early as 1994 since optical resolution was not expected for sub-100nm
features. However, steady improvements and innovations such as Excimer laser sources and immersion photolithography
have allowed some manufacturers to build 22nm CMOS SOCs with single-exposure optical lithography.
With the transition from random complex 2D shapes to regular 1D-patterns at 28nm, the "lines and cuts" approach can
extend CMOS logic to at least the 7nm node. The spacer double patterning for lines and optical cuts patterning is
expected to be used down to the 14nm node. In this study, we extend the scaling to 18nm half-pitch which is
approximately the 10-11nm node using spacer pitch division and complementary e-beam lithography.
For practical reasons, E-Beam lithography is used as well to expose the "mandrel" patterns that support the spacers.
However, in a production mode, it might be cost effective to replace this step by a standard 193nm exposure and
applying the spacer technique twice to divide the pitch by 3 or 4.
The Metal-1 "cut" pattern is designed for a reasonably complex logic function with ~100k gates of combinatorial logic
and flip-flops. Since the final conductor is defined by a Damascene process, the "cut" patterns become islands of resist
blocking hard-mask trenches. The shapes are often small and positioned on a dense grid making this layer to be the most
critical one. This is why direct-write e-beam patterning, possibly using massively parallel beams, is well suited for this
task. In this study, we show that a conventional shaped beam system can already pattern the 11nm node Metal-1 layer
with reasonable overlay margin.
The combination of design style, optical lithography plus pitch-division, and e-beam lithography appears to provide a
scaling path far into the future.
Double Patterning Technology (DPT) is now considered as the mainstream technology for 32 nm node lithography. The main DPT processes have been developed according targeted applications: spacer and pitch splitting either by dual line or dual trench approaches. However, the successful implementation of DPT requires overcoming certain technical challenges in terms of exposure tool capability, process integration, mask performance and finally metrology (1, 2). For pitch splitting process, the mask performance becomes critical as the technique requires a set of two masks (3).
This paper will focus on the mask impact to the global critical dimension (CD) and overlay (OVL) errors for DPT. The mask long-distance and local off target CD variation and image placement were determined on DP features at 180 nm and 128 nm pitches, dedicated to 45 nm and 32 nm nodes respectively. The mask data were then compared to the wafer CD and OVL results achieved on same DP patterns.
Edge placement errors have been programmed on DP like-structures on reticle in order to investigate the offsets impact on CD and image placement. The CD lines increases with asymmetric spaces adjacent to the drawn lines for offsets higher than 12 nm, and then have been compared to the corresponding density induced by individual dense and sparse symmetric edges and have been correlated to the simulated prediction. The single reticle trans-X offsets were then compared to the impact on CD by OVL errors in the double patterning strategy.
Finally, the pellicle-induced reticle distortions impact on image placement errors was investigated (4). The mechanical performance of pellicle was achieved by mask registration measurements before and after pellicle removal.
The reticle contribution to the overall wafer CD and OVL errors budgets were addressed to meet the ITRS requirements.
Double patterning (DP) is today the accepted solution to extend immersion lithography to the 32 nm node and beyond.
Pitch splitting process and spacer process have been developed at CEA-LETI-Minatec. This paper will focus on the
optimization of dry etching process to achieve these two patterning techniques. For each approach, we first discuss the
choices of the starting integration flows based on the requirements to etch the final devices. Then, we develop how the
etching steps were optimized to get a good step by step CD control for 45nm/45nm features.
Double patterning (DP) is today the main solution to extend immersion lithography to the 32 nm node and beyond. Pitch
splitting process with hardmask transfer and spacer process have been developed at CEA-LETI-Minatec. This paper
focuses on experimental data using dry ArF lithography with a k1 factor of 0.20 ; the relative impact of each DP step on
overlay and CD uniformity budgets is analyzed. In addition, topography issues related to the presence of the patterned
hard mask layer during the second imaging step is also investigated. Tool-to-itself overlay, image placement on the
reticle and wafer deformation induced by this DP process are evaluated experimentally and resulting errors on CD
budget have been determined. CD uniformity error model developed by Nikon describing the relationship between CD
and overlay in different DP processes is validated experimentally.
The problem of the alignment tree for double patterning (DP) is presented. When the 2nd DP exposure is aligned to the
underlying zero layer, the space CD uniformity is shown to be well outside the budget for the 32 nm HP node. Aligning
the 2nd DP layer to the zero layer gives better overlay results, but aligning the 2nd DP pattern to the 1st DP pattern gives
results well within the overlay requirements for the 32 nm HP. Aligning the 2nd DP layer to the 1st DP layer is
recommended to give the best CD uniformity and overlay results. Experimental results show, qualitatively, the CD
uniformity is significantly worse when the 2nd pattern is aligned to the zero layer, but the overlay for both alignment trees
could be corrected to roughly the same levels. The raw overlay data shows a significantly different signature for the two
alignment trees, possibly caused by alignment mark signal differences between the marks on the zero and 1st layers, or
distortion of the zero layer after the first etch. The requirements for a DP exposure tool were reviewed and can be
summarized as improved dose control, improved overlay performance, and significantly higher throughput.
Double patterning (DP) has now become a fixture on the development roadmaps of many device manufacturers for half pitches of 32 nm and beyond. Depending on the device feature, different types of DP and double exposure (DE) are being considered. This paper focuses on the requirements of the most complex forms of DP, pitch-splitting (where line density is doubled through two exposures) and spacer processes (where a deposition process is used to achieve the final pattern). Budgets for critical dimension uniformity and overlay are presented along with tool and process requirements to achieve these budgets. Experimental results showing 45-nm lines and spaces using dry ArF lithography with a k1 factor of 0.20 are presented to highlight some of the challenges. Finally, alternatives to DP are presented.
Double patterning (DP) has now become a fixture on the development roadmaps of many device manufacturers for half
pitches of 32 nm and beyond. Depending on the device feature, different types of DP and double exposure (DE) are
being considered. This paper focuses on the requirements of the most complex forms of DP, pitch splitting, where line
density is doubled through two exposures, and sidewall processes, where a deposition process is used to achieve the final
pattern. Budgets for CD uniformity and overlay are presented along with tool and process requirements to achieve these
budgets. Experimental results showing 45 nm lines and spaces using dry ArF lithography with a k1 factor of 0.20 are
presented to highlight some of the challenges. Finally, alternatives to double patterning are presented.
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