Given that the energy of photons in Extreme Ultraviolet (EUV) is significantly higher than in Deep Ultraviolet (DUV), EUV photoresists undergo exposure via photo-ionization. In this process, high-energy photons are absorbed by the photoresist, which ionizes the polymer and subsequently generates photoelectrons. These photoelectrons produce more secondary electrons through scattering. Furthermore, compared to DUV, the number of incident photons in EUV is fewer for the same exposure dose, leading to more significant stochastic effects, such as Line Edge Roughness (LER). Therefore, modeling these stochastic effects in EUV is a noteworthy issue. Due to the complexity of the secondary electron scattering, it is extremely challenging to establish a strict EUV stochastic model from first principles. The current approach to simulating the stochastic behavior in EUV photoresist is primarily conducted through Monte Carlo dynamics-based stochastic methods, which have been proven to be an accurate method. However, these approaches necessitate conducting repeated simulations to obtain the statistical distribution of LER, which can be time-consuming. Using a semi-empirical approach to equivalently process secondary electron scattering is a worthwhile method. In this paper, we employ the Gaussian function to equivalently process the energy distribution after the scattering of secondary electrons. Subsequently, based on the PEB model that incorporates physical mechanisms, the statistical distribution of LER is derived through the transmission of variance. The model is calibrated using the statistical results of the Monte Carlo dynamics-based stochastic methods. The result shows that this approach can quickly predict the statistical distribution of LER in EUV with high accuracy.
Extreme ultraviolet (EUV) lithography is one of the essential technologies for the 5nm and below technology nodes. However, the presence of aberrations in the system severely affects the exposure results, which can lead to wafer rework and increase costs. In order to investigate the impact of aberrations in EUV lithography systems on exposure results, this paper conducts research on the impact of aberrations on exposure results of patterns that commonly used in EUV single-exposure for the 5nm technology node. A large number of aberration experiments are performed, and the distribution of critical dimension (CD), normalized image log-slope (NILS), Pattern Shift (PS), and process variation band (PVB) of exposure results in relation to all Zernike terms variation within ±50mλ is statistically analyzed. We find that aberrations lead to worse exposure results generally, and the distribution of results does not strictly follow a Gaussian distribution but exhibits significant "tail" phenomena. And the impact of aberrations varies for different patterns. Furthermore, the relationship between the distribution of exposure results and the magnitude of aberrations are investigated. It is observed that as the aberration RMS increases, the probability of deteriorated exposure results also increases. Spherical aberration has a significant impact on CD and PVB, while x-direction coma has a significant impact on the PS of vertical line-space patterns, and y-direction coma has a significant impact on the PS of vertical tip to tip patterns. X-direction astigmatism has a higher probability of causing positive PS, while y-direction astigmatism has a higher probability of causing negative PS. Relatively speaking, the effects of 3-foil, 4-foil, and 5-foil aberrations are smaller. This paper provides a clear reference for the influence of various aberrations on exposure results and can contribute to the future development and aberration control of lithography systems.
In EUVL, aberrations play a crucial role in critical dimension (CD) and pattern shift (PS) errors. It is significant to decide aberration compensation and optimization strategies for compensating exposure errors. The modeling process of aberration is time-consuming, mainly because of the need to consider numerous aberrations. In order to save the runtime for aberration modeling, this paper proposes a methodology for identifying the key aberrations that have significant impacts on imaging results. Three different techniques are employed and compared, including single parameter sensitivity analysis, definitive screening design (DSD) method, and SOBOL method that consider the coupling effects of different orders. By comparing the deviations between the imaging results considering only key aberrations and all aberrations, it is found that the identified aberrations achieve extremely high accuracy for various patterns and illumination conditions. Even though the proportion of key aberrations among all aberrations is only a small fraction. All the three methods can achieve that the average CD and PS deviations do not surpass 1%, using 40% of the total 37 aberration items. Thereby, the feasibility of using identified key aberrations for aberration modeling is validated. In addition, we also compare the accuracies of three techniques under the same conditions and found that the SOBOL method is the most suitable technique for identifying key aberrations. Consequently, for specific illumination conditions and corresponding layout patterns, the use of key aberrations is an effective way to characterize the impacts of all 37 aberrations, accelerating the aberration compensation and optimization without sacrificing accuracy.
BackgroundThe resist model is a significant element of computational lithography. Accurate calibration of the resist model is essential to obtain predictive results that closely match the exposure results on wafers. The trade-off between model accuracy and runtime is a challenging task. The selection of critical patterns used in model calibration affects these two metrics directly.AimHaving a dependable method for choosing critical patterns during resist model calibration is essential for lithography engineers with diverse professional backgrounds. Equally important is the ability to decrease runtime while maintaining the precision of calibrated resist models. To address these concerns, we present an approach for selecting critical patterns utilized in resist model calibration.ApproachSince the spectrum carries pattern information, critical patterns are selected based on the coverage of the spectrum in the frequency domain. The spectrum coverage (SCO) of each pattern in the entire test pattern set is calculated according to the frequency and amplitude of all the spectra. Combinations of critical patterns are selected based on their SCO values. The optimal combinations include the most types of spectra and aim to adapt the calibrated model for broad applicability, encompassing both universal and unique patterns.ResultsThe model verification results are compared with the experience-based methods, which select critical patterns based on the pitch-to-CD ratio. The accuracy and effectiveness of the proposed methodology have been demonstrated through experimental results. Compared with experience-based methods that only have dense and isolated critical patterns, our proposed method has a 9.8% increase in accuracy and a 35% decrease in runtime. Even compared with experience-based methods that include forbidden pitches, our method still achieves a 6.4% increase in accuracy without increasing runtime.ConclusionsIn summary, the suggested approach for selecting critical patterns based on SCO surpasses the experience-based methods in terms of both accuracy and efficiency. It can significantly shorten the modeling cycle of resists.
Extreme ultraviolet (EUV) double patterning (DP) with a numeric aperture (NA) of 0.33 can be introduced for the critical via layers at 3nm logic node. The minimum center to center (C2C) distance of a via pattern may form bridging defects even adopting EUV DP. The implemented via process, pattern shifts induced by EUV illuminator, overlay capability and OPC strategies may lead to bridging defects in EUV DP process. This paper will put forth a compact model to detect potential bridging hotspots and predict the corresponding probability of failure considering aforementioned process variations. The feasible design, patterning solutions, and process parameters can be optimized and compensated quantitatively to avoid design updates and mask rebuild.
Source mask optimization (SMO) is one of the most widely employed techniques at 7nm technology nodes. As new lithography techniques develop, lithography metrics of SMO used in cost functions (CF) are also developing quickly. Besides the standard critical dimension (CD) and edge placement error metrics, image log-slope (ILS) and ILS-DOF are also significant, which are penalties in SMO CF. A novel contrast-aware SMO is proposed in this paper to improve ILS in current edge placement error (EPE) based SMO flow. The target ILS, an appropriate penalty weight and the cutlines which should be applied the specific process window metric should be adjusted in several SMO iterations. The corresponding mask optimization results based on the qualified SMO model may provide a qualified retargeting strategy at the same time.
Hotspot detection focused on lithography induced defects becomes crucial at advanced node due to the increasing complexity of the design and manufacture process. Compared with traditional lithography simulation techniques for hotspot detection, machine-learning-based methods have shown significant advantages attributing to the efficiency and generality of their model. However, most convolutional neural network-based hotspot detector can only inference a layout pattern at once. Therefore, sampling clip patterns from the detected layout is the bottleneck of the whole process and determines the performance of hotspot detection. We designed a flow to generate filter rules by clustering analysis of known hotspots, which can efficiently extract layout clips as detected samples to hotspot classifier. We further propose a feature parametric optimization method to extract valuable graphic features for classifiers and reduce redundancy from context patterns. Experimental results demonstrate that these techniques improve the accuracy of hotspots detection.
It is possible to plan mass production by multiple patterning technology of 193 immersion scanner at 7nm technology node. Source mask optimization (SMO) is essential for critical layers, which is a long-running job. It is practicable to explore the methodology to shorten the iterative process of SMO. The different initial sources for SMO of freeform source have little impact on runtime, final source shape and process window (PW) because the algorithm tries to avoid getting stuck in a local optimal solution. However, the number of patterns involved in SMO has obvious positive correlation with runtime. Our paper put forward a novel acceleration workflow for reducing the number of candidates in SMO to reduce the total runtime, and get qualified overlapped PW and improve optimization efficiency. The proposed methodology is demonstrated on leading logic technology node. The results show the feasibility to apply the method for runtime decrease and performance improvement.
With the VLSI technology shrinking to 7nm and beyond, the Redundant Local Loop (RLL), also known as via pillar, becomes a promising candidate of redundant via insertion due to its compatibility with the unidirectional layout style. Existing RLL insertion approaches only leverage rule-based heuristics for manufacturing constraints, which can no longer obtain a large enough Process Window (PW) in advanced technology nodes. It is imperative to develop new techniques to optimize lithography process window while inserting RLL to achieve a good yield. In this paper, we propose a machine learning-based litho-aware RLL insertion framework. Conventional lithography simulation requires tremendous computational resources to evaluate the lithography quality accurately, which is not feasible for process window exploration. We formulate the lithography simulation as a regression task and develop a customized Conventional Neural Network (CNN) architecture to predict the Depth of Focus (DOF), a standard metric for evaluating process window. We propose a complete ow for litho-aware RLL insertion based on the CNN model for process window evaluation. The commercial lithography simulator evaluates the effectiveness of the proposed framework. Experimental results demonstrate that our lithography model can predict the DOF with high accuracy and generalize well on unseen patterns while achieving orders of magnitude speedup compared to conventional lithography simulation. Our litho-aware RLL insertion framework can effectively improve the lithography process window with comparable runtime and insertion rate compared to the state-of-the-art method.
Background: In datasets for hotspot detection in physical verification, data are predominantly composed of non-hotspot samples with only a small percentage of hotspot ones; this leads to the class imbalance problem, which usually hinders the performance of classifiers.
Aim: We aim to enrich datasets by applying a data augmentation technique.
Approach: We propose a data augmentation flow-based generative adversarial network (GAN) to generate high-resolution hotspot samples.
Results: We evaluated our flow with the current state-of-the-art convolutional neural network hotspot classifier by comparison with conventional data augmentation techniques. Experimental results demonstrate that the accuracy improvement of our work can reach 3% at the same false alarm rate and the false alarm rate reduction can reach 5% at the same accuracy.
Conclusions: Our study demonstrates that rational hotspot classification can improve the efficiency of data. It also highlights the potential of GAN to generate complicated layout patterns.
Background: As semiconductor technologies continue to shrink, optical proximity correction may not have enough space to optimize layout due to limitations from adjacent layers. Lithography friendly design (LFD) becomes a powerful tool to detect potential lithography yield killers for fabless side from 14-nm technology node and beyond. Design layout can be modified before tape-out to avoid future rework. However, huge runtime is the bottleneck of LFD.
Aim: Our paper puts forward an innovative layout decomposing algorithm to accelerate LFD at full-chip level.
Approach: The proposed projection-based high coverage fast (PBHCF) LFD layout decomposing algorithm partitions the full-chip layout as a set of unique patterns. The simulation runtime can be reduced by only simulating every unique pattern and corresponding optical interaction range in full chip. The LFD hotspots will be classified, analyzed, and repaired by pattern matching in batches for full-chip layout.
Results: The experiments compare hotspot accuracies and prediction speeds of proposed PBHCF LFD and the most commonly used accelerated algorithm, Smart LFD, for different layouts at chip level for metal 2 layer of 12-nm technology node with pure unidirectional routings. On one hand, the average accuracy of PBHCF LFD can achieve 97.07%, improving 3.4% than Smart LFD on average. On the other hand, PBHCF LFD improves the average prediction speed over regular LFD 19.51%. And the PBHCF LFD is faster than Smart LFD by 5.96%.
Conclusions: PBHCF LFD achieves higher accuracy and less runtime than Smart LFD. The verification experiments conducted on layouts at chip level show the feasibility of the proposed methodology.
It is possible to achieve mass production by multiple patterning technology combing with 193 immersion scanners at 7nm technology node. The application of freeform illumination source shapes is a key enabler for continued shrink using 193 nm immersion lithography with 1.35 NA. Source and mask optimization (SMO) is the important resolution enhancement technique (RET) to optimize a satisfied freeform source. Design pattern library can be used to cognize, manage and compare all the continuous changing and iterative physical designs. Our proposed methodology can improve SMO performance by taking advantages of post-color design pattern library and pattern selection method. And process window limiters are the important guidance to optimize parameters of SMO.
With the development of process technology nodes, hotspot detection has become a critical process in integrated circuit physical design flow. The machine learning-based method has become a competitive candidate for layout hotspot detector with easy training and high speed. Classic methods usually define hotspot detection as a binary classification problem. However, the designer hopes to further divide the hotspot patterns into a series of levels according to their severity to identify and fix these hotspots. In this paper, we designed a multi-classifier based on the convolutional neural network to realize the detection of various levels of hotspot patterns. Unlike classic cross-entropy loss, we proposed a custom loss function to reduce the difference between false predicted levels and corresponding true levels, reducing the adverse effects caused by misclassified samples. Experimental verification results show that our hotspot detector can correctly classify various hotspots levels and has potential advantages for physical designers to fix hotspots.
Features in forbidden pitch have limited exposure latitude and depth of focus in lithography exposure. This paper provides an analysis of forbidden pitch in extreme ultraviolet lithography (EUVL) from the perspective of rigorous simulation and source mask optimization (SMO). In the stage of rigorous simulation, S-litho is used to analyze the normalized image log slope (NILS) of test patterns from different critical layer in 5nm node. Then the process windows of these test patterns are simulated and compared by the lithography simulator Proteus WorkBench. From the result analysis, the forbidden pitches of critical layer in 5nm node are summarized. In addition, the strategy of mitigating the negative effect of forbidden pitch is proposed with the help of computational lithography.
KEYWORDS: Optical lithography, Immersion lithography, Lithography, Photomasks, Source mask optimization, Manufacturing, Overlay metrology, Data processing, Standards development, Back end of line
In the early stage of technology node definition and process development, design house owns abundant logic patterns resources and is able to offer fab more potential hotspots to do process window check, accelerating design rule qualification, feedback and optimization. A systematic methodology has been put forward to detect potential hotspots categories and modify related design rules with very insufficient process information for fabless side. It is efficient to conduct the study on a small number of patterns which can be treated as the typical of the whole physical design. Hence the physical design can be managed as a library and grouped by specific pattern signature for every layer. Based on the connectivity of source drain layers and local-interconnect layers, via0, under the first metal layer, is adopted litho-etch (LE) x4 on 193i scanner as the lithography solution. The experiment is carried out on the via0 layer. With consideration of minimum size and multiple limitations of other layers in design rule, systematic pattern analysis, fuzzy pattern search for low NILS, high MEEF and large PV bands have been combined to optimize the related design rules.
Design technology co-optimization (DTCO) is one of the most critical considerations for yield breakthrough and product ramp-up during the life cycle of a new technology node. Traditional sign-off flow of physical verification cannot guarantee manufacturability totally. Comprehensive design for manufacturing (DFM) check should be involved in flow of product tape-out in order to recognize the patterning and other process challenges which would limit the wafer yield. The process related hotspots were pre-defined with the aid of process related simulation kits on cell, block as well as full chip levels. A systematic DTCO methodology including fabless process friendly flow with lithography friendly design (LFD), pattern match and chemical mechanical planarization (CMP) check, resolution enhancement technology (RET) synthesis, process window check for sensitive patterns as well as weak pattern library assisted circuit diagnosis was as an example of DTCO application at 14/12nm in this paper.
Via location and metal coverage have direct correlation. Optical proximity correction (OPC) always do selective sizing for metal to offer enough via enclosure, such as extending line end or doing external expansion for related metal edge. Hence via poor landing or metal bridging are both potential hotspots. For 14nm technology node and below, process related weak patterns are highly correlated with via locations and corresponding metal dimensions. A via optimization methodology has been put forward to enhance the robustness of design for physical design in fabless. With the aid of lithography check, the yield killers with high potential relativity with vias will be conducted root cause analysis. This paper describes the main solutions for fabless, including pin location blockage, via shift, via shape change, metal sizing change and so on within design rule check (DRC) constraints. The simulation experiment results prove the effective of these solutions due to related simulated yield killers being eliminated.
Standard cell library is the basic for building blocks and SoC (system on chip). And design in current standard cell library always meets the most critical design rule, leading to tight lithography process window and hotspots easily. Besides, passing design rule check (DRC) cannot fully guarantee manufacturability. Lithography simulation check is an essential check item before tape out. It is significant to qualify the standard cell library at the most possible early stage in order to avoid design rework during the tape-out stage. For 14nm technology and below, hotspots appear both inside cell, abut regions of standard cells and pins for routing. Therefore, our paper puts forward a fast DFM-driven standard cell qualification approach to detect the hotspots inside cell and the potential defects from special kinds of pins and abutting standard cells. It can discover problems early and set constraints for placement and routing as early as possible for a fast product yield ramp-up.
Background: As semiconductor technologies continue to shrink, the growth in the number of process variables and combined effects tighten the overall process window, which leads to a more serious yield loss. Yield cannot be totally guaranteed by design rule check and verifications of optical proximity correction, due to complex process variations. The joint effects from unreasonable designs and unstable control of critical dimensions and overlay mainly contribute to the formation of bridging defects in critical interconnect layers. Aim: Our paper puts forward a model to detect the potential bridging region and predicts the corresponding failure probability under a litho-etch-litho-etch process. Approach: The proposed model is based on input error sources from variations of lithography and etch processes. In this scheme, bridging is expected when the minimum space of simulated postetch contours within a specific range is smaller than a user-defined bridging threshold. Gaussian distribution characteristics of line edge roughness (LER) and overlay are considered in the proposed model. Moreover, the proposed model provides meaningful guidelines for bridging prediction with the use of process variation bands. Results: The experiment results indicate consistency and validity of theoretical derivation of the proposed model. The concrete impacts of LER and overlay on the model have been quantitatively analyzed as well. Conclusions: According to the predicted probabilities, the model can early discover potential bridging defects quantitatively by considering the statistical properties of process variations with very few calculations and can give a ranking of failure severity as a decision foundation for design rule optimization.
Use of lithography exposure and metrology tools in production typically results in worse performance than seen on test wafers. Physical design always starts with rough design rule for a new technology node. To evaluate the influence of the inevitable degraded performance on test wafers, our paper put forward a systematic approach to evaluate whether the ability of current process can support the design. The approach utilizes litho-friendly design (LFD) to find the yield killers and conducts pattern classification with pattern matching. Process window discovery (PWD) is used to collect the statistical data to confirm whether the yield killers in LFD simulation will meet the systematic fail on wafer. It is necessary to do mask optimization (MO), source mask optimization (SMO) and design rule optimization (DRO) for the real yield killers. Moreover, design of advanced node may include the patterns inside forbidden pitch range. We do the design rule exploration for metal 2 layer of 14nm technology node and discuss the corresponding solutions for width sensitive zone as well.
The placement and size of SRAF (sub-resolution assisted feature) can greatly affect the overlapped process window. The time-consuming inverse lithography technology (ILT) can provide the co-optimization for both main pattern and SRAFs, which can guarantee the results with high precision. Rule-based SRAF (RBSRAF) offers the efficient application in large scale layout, which relies mostly on the design of test patterns and the corresponding empirical data on wafer. Our paper demonstrates a methodology of SRAF rule extraction and insertion based on ILT. The SRAF rules are extracted from the results of ILT and inserted by the RBSRAF, which ensures the reliability of the SRAF rules and shortens the development cycle. The hotspots areas with substandard process variation (PV) band are then repaired by ILT tools. Besides, the SRAF printing model can further refine the placement and dimension. The experiment results validate the feasibility of our methodology to be applied in large scale layout finally.
The effective test pattern is a crucial component for lithography process optimization such as Source Mask Optimization (SMO) and Optical Proximity Correction (OPC). The conventional parameterized test patterns cannot represent various contexts of patterns, thus sample patterns extracted from layout become an alternative option. This paper introduces a sample patterns extraction method based on the hierarchical clustering algorithm, according to the geometric characteristics. Meanwhile, an improved HLAC-based method is applied to the layout patterns at the stage of feature extraction for accurate characterization. The method can reduce the number of test patterns while maintaining high coverage of layout’s geometric features. The lithography process window is analyzed to validate the effectiveness of the patterns clustering flow. Moreover, the comparison between the spectrums of sample patterns and original layout also indicates that the proposed sampling method preserve a sufficient coverage of layout’s optical characteristics. Pattern extraction method in this paper could provide a candidate solution for fast test pattern generation with high coverage for lithography process exploration.
For 1xnm node and beyond, even Extreme Ultraviolet Lithography (EUV) technology, the serious geometries distortions of the wafer patterns at new process are forcing chipmakers and foundries to utilize model-based SRAFs for ensuring the accuracy and manufacturability of the chips. Model-based Sub-Resolution Assistant Feature (SRAF) is based on inverse lithography (ILT), which is accurate but time-consuming. Therefore, it is necessary to extract the SRAF rules from model-based results and apply them to full chip layout. In this paper, we put forward a methodology of 2D SRAF rule extraction based on model-based results. We can describe and locate the SRAFs by introducing Projection Region, because it reflect the relationship between the SRAFs and main patterns. And the new concept Elongation can make the properties of SARFs more clearly. The experimental results show that the proposed method can extract the 2D SRAFs accurately and output the rules in a general format. The rule simplifying step can decrease the quantity of 2D SRAF rules through the identification and process of symmetry.
As the semiconductor industry enters 20 nm node and beyond, design restrictions and process complexity lay stress on the development for a new technology node. This paper introduces a hybrid hotspot library building method based on simultaneous optical and geometry analysis, which could help explore design rule optimization and enhance cycle time at early stage for new node development. Lithography simulation results verify the accuracy of this method. This method provide a feasible way to build up a preliminary Design Rule Checking (DRC) library even before process-freezing.
With the shrinking of critical dimension, the demand for a process window has reached a new level, which is denoted as the depth of focus at certain exposure latitudes. Therefore, high-quality monitoring and controlling of focus shift are becoming more and more critical. With the purpose of providing an optimal focus monitoring mark, which can be applied in freeform or off-axis illumination with a big sigma and hypernumerical aperture (NA) scheme, a global optimization method combined with the idea of a genetic algorithm is developed. For illustration, two optimal mask structures under quasar and freeform illumination conditions are given by the optimized method. The numerical simulations with the lithography simulator PROLITH are provided to demonstrate the performances of these two structures. In addition, the robustness of these optimized structures is analyzed by considering the phase-shift error in mask manufacturing. The above simulation results verify the effectiveness and validity of the proposed optimization methodology and also show that the mask structure provided by the optimized method has the potential to be an efficient candidate for measuring the defocus of scanners in the immersion lithography with hyper NA.
We demonstrate two different approaches of implementing design technology co-optimization (DTCO). One is on optimizing standard cells. Before being placed on mask, standard cells can be evaluated and optimized to gain better process windows. This approach enables an additional learning cycle before mask tapeout, reducing process development cost. The other approach uses a random pattern generator to create various patterns with high coverage based on given design rules. Lithography simulation is used to evaluate process window of these patterns, and annotates its printability. Test patterns generated in this way can be used for early process development.
ASML AH53 and AH74 with higher odd-order diffraction light are the widely used alignment marks in industry to achieve better alignment accuracy by reducing mark damage noise. During lithography alignment process, decent diffraction light power is the basic demand. However, with the use of some high absorption (k is not equal to 0 for detective wavelength) material, it is difficult to detect the light power reflecting from the thick and opaque film stacks with these standard alignment marks. Here we optimized four alignment marks with higher odd-order diffraction power with comparing with AH53 and AH74. One software based on Fourier optical theory is built to quickly calculate the wafer quality (WQ) of different film stacks and different alignment marks. ASML SMASH alignment system can accept customized alignment mark, with new mark type configuration file. In order to demonstrate the effectiveness of new alignment marks, we put the marks on a mask and do the experiments to compare with simulation results. All the experiments results show that new designed alignment marks have larger WQs of odd-order diffraction.
This paper proposes a novel hotspots fixing flow, in which design rule optimization and lithography RET solution are obtained simultaneously. This flow is most effective in the early development phase, and its methodology is rooted from design technology co-optimization (DTCO). Two layout files, corresponding to separate colors of a double-pattern layer (10nm node M1), are first generated by a pattern generator, and they meet no-stitching requirements and are design rule check (DRC) clean. Then, source, mask and design rule co-optimization is done with the layouts, and the design rules are optimized to remove hotspots and enable maximum lithography process window (PW). The mask optimization (MO) in combination with cost function manipulation and design rule optimization improve the robustness of initial design rule. The application of the methodology illustrates a friendly design rule and avoids later design rework.
As the fin based field effect transistors (Fin-FET) emerge, the device structure is changed from two dimensional to three dimensional. Due to the existence of topography, the lithographic performance may be affected and, in most cases, becomes more complicated, especially in the ion implantation process after gate being constructed. In this paper, the various parameters that may have influence on the resist topography are being investigated, such as the density, height, and corner rounding of the fin structures, the height, and the corner rounding of the gates, etc. Theoretical analysis shows that the resist image intensity among the fins and gates can be improved by increasing the thickness of the oxide on the edge of the gate. Following the above theoretical analysis, a method for lithographic performance improvement with the existence of resist topography is proposed. The method is demonstrated from the simulations with the lithography simulator PROLITH. With an optimal thickness of oxide on the surface of gate, the residual resist in the topography after development will be removed thoroughly. Compared with other methods, the proposed method requires neither a specific system setup nor an additional etch process, which is a tremendous cost-saving in mass production.
Typically, the printing of contact patterns uses a dark-field (DF) mask in combination with a positive tone resist and positive tone development (PTD) process. PTD, which has a mature process and simulation model, had been widely applied in high-volume manufacturing. For the low aerial image quality of a DF mask in advanced node, PTD is substituted by negative tone development (NTD), which uses a positive tone resist and bright-field mask. Due to the high cost and immature simulation model of NTD process, it is worthwhile to extend PTD to some critical patterns. With the purpose of improving the resist profile and process window (PW) of the contact pattern with a PTD process in advanced node, an optimization method combined with the idea of a genetic algorithm is put forward. For performance of the optimized resist under the conditions of best focus and best dose, an evaluation based on the through pitch square contact patterns with the critical dimension (CD) fixed at 50 nm has been provided. The generalization performance of the optimized resist is also analyzed by a systematic method, which contains the resist profile and PW simulation on the base of through CD and through pitch contact patterns. The above simulation results verify the effectiveness and validity of the proposed optimization method.
Design and technology co-optimization (DTCO) can satisfy the needs of the design, generate robust design rule, and avoid unfriendly patterns at the early stage of design to ensure a high level of manufacturability of the product by the technical capability of the present process. The DTCO methodology in this paper includes design rule translation, layout analysis, model validation, hotspots classification and design rule optimization mainly. The correlation of the DTCO and double patterning (DPT) can optimize the related design rule and generate friendlier layout which meets the requirement of the 14/10nm technology node. The experiment demonstrates the methodology of DPT-compliant DTCO which is applied to a metal1 layer from the 14/10nm node. The DTCO workflow proposed in our job is an efficient solution for optimizing the design rules for 14/10 nm tech node Metal1 layer. And the paper also discussed and did the verification about how to tune the design rule of the U-shape and L-shape structures in a DPT-aware metal layer.
A new focus monitor mask having novel grating structure is proposed to measure the focus variation of the scanner. The grating pattern composes of transparent line, opaque line, π-phase shift groove and π/2 -phase shift groove with their width ratio equivalent to 1:4:1:2. By using this structure, one of the first order and one of the second order of the diffraction spectrum are eliminated. Therefore, the lithography image is formed by the interference of the zeroth order and the left positive (or negative) 1st and 2nd orders, which is more sensitive to the subtle change of focus. The basic principle and characteristic of the proposed mask is described in this paper. Simulations with the lithography simulator PROLITH shows that the monitoring accuracy is improved more than 25%, compared with the conventional phase grating focus monitor (PGFM). The novel mask proposed in our job has potential to be an efficient candidate for measuring the defocus of scanner in the immersion lithography with hyper NA.
With the development of the lithography, the demand for critical dimension (CD) and CD uniformity (CDU) has reached a new level, which is harder and harder to achieve. There exists reflection at the interface between photo-resist and substrate during lithography exposure. This reflection has negative impact on CD and CDU control. It is possible to optimize the litho stack and film stack thickness on different lithography conditions. With the optimized stack, the total reflectivity for all incident angles at the interface can be controlled less than 0.5%, ideally 0.1%, which enhances process window (PW) most of the time. The theoretical results are verified by the experiment results from foundry, which helps the foundry achieve the mass production finally.
The impact of mask three dimensions (M3D) effect on lithography processes is getting more pronounced from 32 nm nodes1-2. In this paper, we report four research progresses on the M3Deffect. Firstly, the impacts of M3D effect on the best focus (BF) offset were studied with though pitch as test pattern. The M3D effect has negative impacts on the BF, generating the BF offset pattern by pattern. The BF offset strongly depends on MoSi film thickness (THK). However the impact of MoSi profile, or side wall angle (SWA) could be ignored. Secondly, M3D OPC is needed to mitigate the shift of dose and focus center. Thirdly, as long as enough shade, the thinner MoSi, the less BF shift, as electromagnetic field (EMF) effect makes space behave smaller, which leads to higher contrast but higher mask error enhancement factor(MEEF); So the trade-off between contrast and MEEF is needed. And MoSi THK 43.7 nm in production supposed to be the optimized value from this study. Finally, compared to attenuating phase shifting mask (att.PSM) mask, opaque MoSi on Glass (OMOG) mask is more robust in terms of MEEF, the normalized image logarithmic slope (NILS) etc., not obviously influenced by mask duty ratio.
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