Editor-in-Chief Harry Levinson remarks on the significance of the BACUS Symposium.

An expression of the in-photoresist electric field of light from an arbitrary incident angle and the intensity of the image of a grating near the resolution limit of the exposure system are given. For post-development vertical sidewalls, resists with graded absorption coefficents may be helpful. A formula for the absorption coefficient as a function of the depth into the resist is given.

Guest editors Stephen Renwick and Laurent Pain introduce the Special Section on Direct Write Lithography.

Optical direct-write technology has been studied since the successful development of the micromirror-based spatial light modulators in the 1990s. It is expected to have advantages over electron beam direct-write in the viewpoints of higher productivity and common resist process with existing semiconductor manufacturing. In the 2000s, there was an effort to develop an optical direct-write system using deep ultraviolet (DUV) excimer laser and grayscale tilt micromirror devices, aiming at low-volume manufacturing of semiconductor devices. Recently, a new scheme of optical direct-write, called the digital scanner, has been demonstrated. It uses solid-state DUV laser and digitally controlled spatial light modulator. Past development activity of optical direct-write is reviewed with discussion of the merits and demerits of the proposed technological options in the new system, comparing them to past efforts.

Digital scanner (DS), a deep ultraviolet optical maskless exposure tool is being developed. DS uses a micromirror-type spatial light modulator to create the “mask” pattern combined with a solid-state laser with a wavelength of 193 or 248 nm. The exposure concept of DS and advantage of solid-state laser as an exposure light source is described. DS proof-of-concept tool with resolution of half-pitch 80 nm L/S was developed. The exposure results of maskless unique application, such as large area printing and chip ID printing for security purposes, are shown.

Electron beam (E-beam) direct write (EBDW) lithography is a worldwide reference technology used in laboratories, universities, and pilot line facilities for research and development. Due to its low writing speed, EBDW has never been recognized as an acceptable industrial solution, except for optical mask manufacturing. Nevertheless, its natural high-resolution capability allows for low-cost patterning of advanced or innovative devices prior to their high-volume manufacturing ramp-up. Due to its full versatility with almost all types of chemically amplified resists, EBDW is a perfect complementary solution to optical lithography. We demonstrate the compatibility of EBDW lithography with advanced negative tone development resists and the possibility of setting up a hybrid E-beam/193i lithography process flow with high performance in terms of resolution and mix and match overlay. This high-end lithography alliance offers flexibility and cost advantages for device development research and development, as well as powerful possibilities for specific applications such as circuit encryption, as discussed at the end of our study.

The availability of high-resolution and high-throughput lithographic fabrication technologies, such as electron-beam lithography, based on variable shaped beam writing and character projection opens the way for the flexible use of various optical nano-structures for some of the most demanding applications. We discuss the technical features, advantages, and limitations of these pattering approaches and show how they can favorably be combined to realize optical nano-structures for applications, which are as diverse as gratings for ultra-short laser pulses or high-resolution spectrometers, computer generated holograms for asphere testing, various optical meta-structures (lenses and gratings), or UV-polarizers.

Electron beams have been used for lithography since the 1970s. Resolution was never the limitation, but the throughput was. When the so-called next-generation lithography (NGL) solutions were adopted in the 1990s, electron beam and nano-imprint technology were considered alternatives for optical lithography. However, since ASML brought its extreme ultraviolet (EUV) lithography on the market, the NGL of choice seemed to be clear. Two issues remained unsolved: how to make the reticles and, second, how to serve the market for low-volume semiconductor wafer manufacturing for which the EUV solution does not give a commercial viable solution. As multi e-beam has proven to be a successful solution for the reticle writing issue, the question is whether it could also address the second issue. The two main e-beam candidate technologies are compared here in terms of their throughput claims, LWR, and addressing grid as well as their scalability (LEEPL, low-energy electron beam proximity-projection lithography, is not considered, as it is not a maskless technology).

Guest Editors Catherine B. Labelle and Mark J. Kushner introduce the Special Section on Plasma Modeling and Feature Profile Simulation.

Modeling and simulation of feature scale profiles, including damage distributions and film properties in dry etching (continuous wave, pulse, cycle, and atomic layer etching) and deposition processes (chemical vapor, physical vapor, and atomic layer deposition) using string, shock tracking, level-set, and cell removable (or voxel) methods, are useful for predicting process properties and gain insights into the variation mechanisms for realizing high performance of advanced complementary metal-oxide semiconductor devices and have been comprehensively reviewed in this work. The future perspective has also been discussed from the viewpoint of a fusion physical model with machine learning using real-time monitoring of the manufacturing equipment, so-called process informatics. Furthermore, after the introduction of quantum computing for process simulations on atomic scales, the epoch of full digital twins might be realized.

Low temperature plasmas (LTPs) are widely used in the semiconductor industry to etch, deposit, modify, and pattern thin films during the fabrication of integrated circuits. Modeling techniques used to simulate industrial processing plasmas are reviewed in this article. The authors also provide their perspective on areas of highest research and development need. The most common plasma sources used in the semiconductor industry are capacitively coupled plasmas, inductively coupled plasmas, magnetrons, magnetized and unmagnetized microwave plasmas, and remote plasmas. These LTP systems can be simulated using global, fluid, and particle-based kinetic modeling techniques. A variety of hybrid methods have also been developed that supplement fluid plasma models with kinetic models for aspects of the plasma behavior. The industry expects plasma models to be quantitatively accurate, so they can be used as an LTP system design tool. The optimal models are usually a thoughtful blend of precise physics and experimentally guided refinements. The authors highlight the benefit and need of multi-faceted plasma model validation studies in which plasma sources are first characterized using a variety of complementary diagnostics. Quantitatively accurate models for these plasmas are then developed to test the accuracy of key aspects of the plasma including the electron energy distribution function, ion energy distribution function at surfaces, charged and neutral species densities or fluxes, and gas temperature. An important aspect of the validation exercise is the development of the plasma chemistry mechanisms and models for plasma–surface interaction.

Machine learning has had an enormous impact in many scientific disciplines. It has also attracted significant interest in the field of low-temperature plasma (LTP) modeling and simulation in past years. Its application should be carefully assessed in general, but many aspects of plasma modeling and simulation have benefited substantially from recent developments within the field of machine learning and data-driven modeling. In this survey, we approach two main objectives: (a) we review the state-of-the-art, focusing on approaches to LTP modeling and simulation. By dividing our survey into plasma physics, plasma chemistry, plasma–surface interactions, and plasma process control, we aim to extensively discuss relevant examples from literature. (b) We provide a perspective of potential advances to plasma science and technology. We specifically elaborate on advances possibly enabled by adaptation from other scientific disciplines. We argue that not only the known unknowns but also unknown unknowns may be discovered due to the inherent propensity of data-driven methods to spotlight hidden patterns in data.

Guest editor Alexander Starikov introduces the Special Section on Control of Integrated Circuit Patterning Variance, Part 5: Pattern Placement, Critical Dimension, and Edge-to-Edge Overlay.

With the multiple patterning schemes and recent introduction of EUV lithography, there is a clear need to fully characterize the edge placement error (EPE) budget in the technology development, and if this information is available in-line, use this information for process control. This methodology has been currently applied to the EUV characterization where the overlay (OVL) and local linewidth roughness (LWR) variations contribute the most to the EPE budget. We describe EPE metrology techniques based on design for inspection™ (DFI) methodology, with non-contact electrical measurements of spatial interactions between integrated circuit (IC) elements created with different patterning and manufacturing steps. Specially designed sub-micron scale test structures are placed within the product die (in place of the filler cells and dummy fill without any area penalty), as well as in the scribe lines, which allows for the EPE monitoring with sub-design rule designs. All DFI structures are tested with a custom (designed and manufactured by PDF) eBeam voltage contrast tool with a very high speed and sub-nm resolution. This methodology has been currently applied to the EUV characterization where the OVL and local LWR variations contribute the most to the EPE budget. In this work, we describe and illustrate the DFI methodology application for the EPE and process window characterization and control.

We have used large-field-of-view voltage contrast metrology to determine the design rules on a pitch 28 nm single-exposure extreme ultra violet dual damascene process, and to study a use case in which two design parameters, metal tip-to-tip critical dimension and via-to-line placement, interact nontrivially in the yield determination. By designing proper test structures, it is possible to determine the different failure mechanisms for the given process integration and determine the patterning cliffs and design rules.

E-beam inspection based on voltage-contrast (VC) defect metrology has been widely utilized for failure mode analysis of memory devices. Variation in e-beam image contrast indicates shorts, opens, and void defect inline inspection in the idle of production line. Meanwhile, accurate measurement of threshold voltage and the source–drain current is required to characterize memory cell through multilayers. However, in the subthreshold region of memory cell, VC is weakened due to gate voltage stimulated by electron dose of e-beam scanning. We developed a modulated beam imaging with the SEM vector scan system to enhance VC contrast and defect inspection capability. Reliability of the modulated electron microscopy is validated by comparing with physical probing test result for process variation of Boron doping and annealing conditions in full wafer processing. VC with the modulated electron microscopy is well correlated to the probing test result. Image contrast of the modulated microscopy can differentiate contact via on floating circuit and disconnected floating circuit. We applied the modulated electron microscopy for inline electrical defect detection at the middle of manufacturing line of integrated circuits. The defect distribution map by the modulated electron microscopy was confirmed to reproduce the physical probe test result. By achieving inline electrical characterization before back end of line, yield loss issues can be detected and characterized 2 weeks earlier than conventional method. Moreover, this ability to detect and characterize memory cell issues inline is supposed to contribute to overcome the yield learning cycle bottleneck.

With recent technology advancements of multi-beam mask writers, curvilinear masks can now be extended to advanced EUV lithography generations. Inverse lithography technology (ILT) is a curvilinear mask-friendly mask synthesis solution with superior quality but slower TAT than mainstream rule-based assist feature + OPC methods. To achieve ILT quality for full-chip layouts, a faster curvilinear ILT-based mask synthesis solution is desired. We present a hybrid curvilinear mask solution with ILT and curve OPC for full-chip EUV layers. Results of full-chip EUV in lithographic performance and runtime are compared among different solutions including traditional Manhattan OPC, curvilinear ILT, and hybrid machine learning (ML) ILT plus curve OPC. Another important factor of curvilinear mask advancement is data volume. We present our curve OPC solution with the cubic Bezier curve to control the data volume of curvilinear masks. The mask writing process is playing an increasingly important role in the overall manufacturing flow. Therefore, we also present an enhanced mask synthesis flow utilizing a mask error correction solution for curvilinear masks written by a multi-beam writer.

In the sub-7 nm technology nodes, the cost of printing dense via layers increases dramatically. Directed self-assembly (DSA) (DSA) technology with multiple patterning (MP) lithography (DSA-MP) provides a high-volume manufacturing solution with a high throughput and low cost. To enable the technology, a high-quality DSA-MP-aware layout decomposer that contains DSA grouping and MP assignment is necessary. We propose a graph-based heuristic algorithm that minimizes the potential DSA decomposition violations using grouping nodes in the complete graph and the corresponding place-and-route method. Then the grouping result is modified and the MP assignment is solved simultaneously by hybrid algorithms. Experimental results show the efficiency and effectiveness of the proposed method in dealing with large dense vias patterns.

A high-numerical-aperture (NA) extreme ultraviolet lithography (EUVL) system has been highly desired and is now under construction at imec-ASML High NA Laboratory in Veldhoven. However, there are still many challenges to realizing high-volume manufacturing by High NA EUVL. Line edge roughness (LER) mitigation is one of the key elements. In our previous research, we studied how the normalized image log slope (NILS) and resist film thickness affect resist LER by exposure at NA 0.33 on NXE:3400 and S-Litho EUV. However, the mask absorber, mask tone, exposure dose, and postexposure bake (PEB) temperature were not the subject of previous investigations for decreasing LER. They have the potential to mitigate resist roughness such as illumination and resist thickness studied previously. Unbiased LER values of metal oxide resists (MOR) were experimentally measured on a half-pitch (hp) 14 nm line and space under several mask absorber/tonality, dose, and PEB temperature values. Per the mask absorber/tone, the NILS was varied using different illumination shapes. Low-n masks exhibited a higher NILS for the same illumination shape, which resulted in lower resist LER on the wafer. It was also found that the mask tone can contribute to LER mitigation. According to detailed investigations about the mask roughness, mask error enhancement factor, and flare by critical dimension scanning electron microscope (CD-SEM) measurements and S-Litho EUV, the most likely reason for the LER difference is a flare increase given by mask tone changes. From the dose and PEB temperature variation study, dose was apparently more dominant in resisting roughness than PEB temperature.

Erratum corrects several errors in mathematical expressions.