Stochastic printing variations are a challenge for EUV lithography and it is well known that these variations worsen if exposed out-of-focus because the EUV image contrast degrades. The introduction of 0.55NA will improve image contrast at a reduced depth-of-focus. This paper will describe how best focus planes differences between features can be used to design focus-sensitive metrology targets that can report EUV focus if used in combination with an optical metrology tool. Moreover, the developed target methodology ensures design rules compliance. The focus metrology target concept is experimentally demonstrated using a 24nm pitch line/spacer in combination with a low-n EUV mask absorber material, metal-oxide-resist (MOR), and a 0.33NA EUV scanner. The observed focus variation is modeled to quantify how much content is correctable using scanner feedback. This illustrates that on-product focus metrology can improve focus performance if combined with advanced process control.
State of the art after-develop (ADI) overlay is measured with multi-wavelength micro diffraction-based overlay techniques. A micro diffraction-based overlay target consists of two pairs of gratings, with the same pitch in the top and bottom layer. The gratings in the top layer have a bias offset with respect to the bottom layer in the positive or negative direction. When illuminated, +1st and -1st order light is diffracted. The asymmetry in the intensity of these signals contains the overlay information. In this paper, ADI overlay is measured with a new dark-field target design for ADI overlay. Like a micro diffraction-based overlay target, it consists of pairs of gratings in the top and bottom layer. Instead of a bias offset between top and bottom gratings, different pitches are used resulting in a continuous-bias throughout the grating pair. When illuminated the diffracted light contains moiré fringes, in which the overlay is stored in the phases. This technique has improved accuracy and robustness by design, because it is immune to symmetrical process changes like stack height variations and grating imbalance. Additionally, it shows more stable behavior through wavelength, both in signal strength and overlay. These characteristics make it possible, with a single wavelength, to achieve similar or better performance than micro diffraction-based overlay using a multi-wavelength solution, resulting in higher throughput. This is demonstrated on Samsung’s latest memory node where on average an 21% reduction is achieved in the 3sigma of the mis reading correction with a single-wavelength phase-based overlay measurements, compared to multi-wavelength micro diffraction-based overlay measurements.
Improvements on on-cell overlay is necessary to suppress misalign induced defects. Precise and accurate on-cell overlay measurements are strongly demanded, however, we are facing limitations on conventional CD-SEM based on-cell overlay measurements, such as unexpected overlay bias. To mitigate drawbacks of top view based on-cell overlay measurements, we present voltage contrast based overlay measurements (VCBO) which utilize specially designed cell patterns with combinations of programmed misalignments on scribe lanes, measured by defect inspection equipment, eP5 [1]. We successfully demonstrate the first defect based overlay measurement on DRAM device and a potential of 27% in-die overlay gain is shown. Also, we display overlay process margin at about ~1000 points on wafer. As a definite standard of on-product overlay measurement, this technology will be used for advanced misreading correction (MRC). We believe that the technique would be widely used and become necessary in near future.
In next generation 3D-NAND devices, accurately determining after-etch overlay for the multi-layer stack is a major challenge. This is especially the case for the multi-tier 3D-NAND structures, where the overlay of the channel holes is an important performance parameter. The most commonly used after-etch metrology suffer both from the high aspect ratio of the channel holes and from the potential presence of large tilts.
Using In-Device Metrology (IDM), we show results of non-destructive overlay measurements on 3D-NAND memory holes. Once the overlay signal has been determined, the remaining asymmetry information in the measurement can be used to characterize tilt phenomena densely through the memory array.
Using hyper-dense in-device measurements show the overlay effects of intra-die stress. A new lithography scanner model is used to correct specifically for such intra-die overlay fingerprints.
This paper demonstrates the improvement using the YieldStar S-1250D small spot, high-NA, after-etch overlay in-device measurements in a DRAM HVM environment. It will be demonstrated that In-device metrology (IDM) captures after-etch device fingerprints more accurately compared to the industry-standard CDSEM. Also, IDM measurements (acquiring both CD and overlay) can be executed significantly faster increasing the wafer sampling density that is possible within a realistic metrology budget. The improvements to both speed and accuracy open the possibility of extended modeling and correction capabilities for control. The proof-book data of this paper shows a 36% improvement of device overlay after switching to control in a DRAM HVM environment using indevice metrology.
On-product overlay requirements are becoming more challenging with every next technology node due to the continued decrease of the device dimensions and process tolerances. Therefore, current and future technology nodes require demanding metrology capabilities such as target designs that are robust towards process variations and high overlay measurement density (e.g. for higher order process corrections) to enable advanced process control solutions. The impact of advanced control solutions based on YieldStar overlay data is being presented in this paper. Multi patterning techniques are applied for critical layers and leading to additional overlay measurement demands. The use of 1D process steps results in the need of overlay measurements relative to more than one layer. Dealing with the increased number of overlay measurements while keeping the high measurement density and metrology accuracy at the same time presents a challenge for high volume manufacturing (HVM). These challenges are addressed by the capability to measure multi-layer targets with the recently introduced YieldStar metrology tool, YS350. On-product overlay results of such multi-layers and standard targets are presented including measurement stability performance.
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