Multi-wavelength (MWL) micro diffraction-based overlay (μDBO) is a prominent method for after-develop inspection (ADI) overlay measurements, which is favorable for accuracy and robustness. Continuous-bias DBO (cDBO) is expected to offer robustness improvements against stack variation, asymmetry, and imbalance. In this paper, dual-WL (DWL) cDBO profiles were evaluated to secure the advantages of both of MWL and cDBO applications. The metrics used to evaluate accuracy and robustness of ADI overlay measurements are residual, dynamic precision (DP), and wafer-to-wafer variation of the difference between ADI and after-etch inspection overlay. 70% of DWL profiles had improvements in their residual values comparing with their single-WL (SWL) constituents on Samsung R&D wafers in layer A. On layer B, the best DWL cDBO profiles showed around 5% improved residuals comparing with its SWL constituents. DWL cDBO showed around 30% averaged improved DP compared with SWL counterparts. DP improvements of MWL cDBO are following the expected DP improvements, based on the signal-to-noise ratio improvement with increasing number of signals. Residual improvement with increasing number of WLs is different from the DP improvement, and the best DWL residual improvement is higher than that of SWL measurements with noise reduction techniques applied. This shows that the residual improvement cannot be attributed to the increased number of acquisitions, and that it could be an innate advantage of MWL cDBO.
In this paper the use of the EPE metric directly in the process optimization method for a DRAM use case has been researched. We show that EPE-aware optimization, using scanner dose and overlay control sub-recipes, is outperforming conventional optimization in terms of EPE Dies in Spec. Hence, it can be expected that also device yield can be improved by EPE-aware control.
During metrology overlay recipe setup typically a wide range of different target designs are present to select from. The main goal of recipe setup is to select the most accurate target type-recipe combination at ADI (after develop inspection) without additional external information that can be used for production on a large set of wafers. We will introduce a method based on blind source separation to disentangle the contributions of target asymmetry and the overlay of the targets. Based on this separation, the most accurate target-recipe combination can be selected. On top of selecting the most accurate target-recipe combination, it is important to stabilize the difference between the overlay on device and the overlay as measured on the target. In order to increase that stability we will introduce advanced algorithms in the ADI measurements that use measured asymmetry parameters to correct for inline target asymmetry variation. We will show a metrology to device matching improvement of up to 40% on product wafers.
State of the art after-develop (ADI) overlay is measured with multi-wavelength micro diffraction-based overlay techniques. A micro diffraction-based overlay target consists of two pairs of gratings, with the same pitch in the top and bottom layer. The gratings in the top layer have a bias offset with respect to the bottom layer in the positive or negative direction. When illuminated, +1st and -1st order light is diffracted. The asymmetry in the intensity of these signals contains the overlay information. In this paper, ADI overlay is measured with a new dark-field target design for ADI overlay. Like a micro diffraction-based overlay target, it consists of pairs of gratings in the top and bottom layer. Instead of a bias offset between top and bottom gratings, different pitches are used resulting in a continuous-bias throughout the grating pair. When illuminated the diffracted light contains moiré fringes, in which the overlay is stored in the phases. This technique has improved accuracy and robustness by design, because it is immune to symmetrical process changes like stack height variations and grating imbalance. Additionally, it shows more stable behavior through wavelength, both in signal strength and overlay. These characteristics make it possible, with a single wavelength, to achieve similar or better performance than micro diffraction-based overlay using a multi-wavelength solution, resulting in higher throughput. This is demonstrated on Samsung’s latest memory node where on average an 21% reduction is achieved in the 3sigma of the mis reading correction with a single-wavelength phase-based overlay measurements, compared to multi-wavelength micro diffraction-based overlay measurements.
In multi patterning processes, overlay is now entangled with CD including OPC and stochastics. This combined effect is a serious challenge for continued shrink and is driving down the allowed overlay margin to an unprecedented level. We need to do everything to improve overlay where accurate measurement and control of wafer deformation is extremely important. This requires accuracy in overlay metrology that decouples target asymmetry from wafer deformation. Multiwavelength diffraction-based overlay (DBO) is positioned for providing such accuracy while maintaining the required measurement speed. At the same time, with the increase of process complexity in advanced nodes, several new types of target asymmetries are introduced. Some of such asymmetries vary even within the target / grating area (intra-grating) and some are so severe that it impacts the center of gravity shift of the overlay target.
Utilizing a unique high NA optical system, a new methodology to measure device overlay accurately has been developed with a key differentiation. Historically, optical techniques to measure features below the image resolution require supporting measurement techniques to be used as a reference to anchor the optical measurement. This novel selfreference methodology enables accurate and robust optical metrology for device features after etch eliminating the need for external reference measurements such as Decap, x-sections or high landing energy SEMs. In this paper, we discuss how a high NA Optical Metrology system enables measurements on small area device replica targets, which enables the ability to create a reference target for device measurements. The methodology utilizes this reference target to enable accurate direct on device overlay measurements without the need for an external reference. Furthermore, the technique is expanded to improve the robustness of the measurement and monitor live in production the health of the recipe, ensuring accuracy overtime. This ultimately leads to a method to extend the recipes in real-time based on the health KPIs. The improved accurate and robust device overlay measurements have proven to improve the overlay performance compared to other techniques. This, combined with the speed of optical systems, enables unconstrained dense measurements directly on device structures after etch, allowing for improved overlay control.
In order to meet the tightened lithography performance requirement for EUV systems, a good on-product focus control with accurate metrology is essential. In this manuscript we report on a novel metrology solution for the EUV on-product focus measurement using YieldStar. The new metrology has been qualified on the Logic product wafers and when combined with the advanced techniques and algorithm shows a performance that is accurate and precise enough to meet EUV requirements. Furthermore, the new methodology provides the opportunity for on-product focus monitoring and control through different scanner interfaces. Here we present a case in which the Imaging Optimizer using the EUV metrology data shows an improvement of over 20% on the focus uniformity.
In leading edge patterning processes, overlay is now entangled with CD including OPC residuals and stochastics. This combined effect is a serious challenge for continued shrink and can be characterized with an Edge Placement Error (EPE) budget containing multi-domain components: global and local CD, local placement errors, overlay errors, etch biases and OPC. EPE defines process capability and ultimately relates to device yield. Understanding the EPE budget leads to efficient ways to monitor process capability and optimize it using EPE based process control applications. We examine a critical EPE use case on a leading edge DRAM node. We start by constructing and verifying the EPE Budget via densely sampled on-product in-device local, global CD and Overlay metrology after the etch process step. EPE budget contributors are ranked according to their impact to overall EPE performance and later with simulated EPE performance improvements per component. A cost/benefit analysis is shown to help choose the most HVM-friendly solutions.
Overlay is one of the key factors which enables optical lithography extension to 1X node DRAM manufacturing. It is natural that accurate wafer alignment is a prerequisite for good device overlay. However, alignment failures or misalignments are commonly observed in a fab. There are many factors which could induce alignment problems. Low alignment signal contrast is one of the main issues. Alignment signal contrast can be degraded by opaque stack materials or by alignment mark degradation due to processes like CMP. This issue can be compounded by mark sub-segmentation from design rules in combination with double or quadruple spacer process. Alignment signal contrast can be improved by applying new material or process optimization, which sometimes lead to the addition of another process-step with higher costs. If we can amplify the signal components containing the position information and reduce other unwanted signal and background contributions then we can improve alignment performance without process change. In this paper we use ASML's new alignment sensor (as was introduced and released on the NXT:1980Di) and sample wafers with special stacks which can induce poor alignment signal to demonstrate alignment and overlay improvement.
Overlay metrology target design is an essential step prior to performing overlay measurements. This step is done through the optimization of target parameters for a given process stack. A simulation tool is therefore used to improve measurement performances. This work shows how our Metrology Target Design (MTD) simulator helps significantly in the target design process. We show the role of film and Optical CD measurements in improving significantly the fidelity of the simulations. We demonstrate that for various target design parameters we are capable of predicting measured performance metrics by simulations and correctly rank various designs performances.
In this paper, set of wafers with separated processes was prepared and overlay measurement result was compared in two methods; IBO and DBO. Based on the experimental result, theoretical approach of relationship between overlay mark deformation and overlay variation is presented. Moreover, overlay reading simulation was used in verification and prediction of overlay variation due to deformation of overlay mark caused by induced processes. Through this study, understanding of individual process effects on overlay measurement error is given. Additionally, guideline of selecting proper overlay measurement scheme for specific layer is presented.
In this study, we proposed the concept of high order field-by-field correction for Matched Machine Overlay (MMO)
error minimization and we have validated it through experiments. Because scanners have unique grid fingerprint, MMO
value between machines is higher than the one of Single Machine Overlay (SMO). In some cases, the localized grid
distortion mainly contributes to the MMO value. However, this localized grid distortion cannot be flatten by a normal
correction method such as 10-parameter correction. Until now, in order to flat the localized grid distortion, ultimate
correction capability can be realized by combining 6-parameter field-by-field correction and intra-field high order
correction methods. However 6-parameter could be not enough to follow the diversity of local distortion. In this study,
for further improvement of MMO, high order field-by-field correction capability was investigated and the results were
compared. Base on simulation, we found that the field-by-field correction was a successful way to lower the MMO value
of EUV vs. ArF immersion scanners. By experimental demonstration, it showed that field-by-field correction was more
effective to correct localized grid distortion and the gain via high order model was about 0.5 nm. These results will be
helpful to achieve the MMO specification for the next generation device.
The shrinkage of design rule necessitated corresponding tighter overlay control. However, in advanced applications, the
extension of current technology may not be able to meet the control requirement, consequently, additional breakthroughs
are required. In this study, we investigated methods to enhance the overlay control, approaches by extraction of real
overlay error out of overlay measurement. So far, only the destructive inspections like vertical SEM have enabled us to
measure real misalignment. But, a concept of non-destructive method is proposed in this paper, extracting vertical
information from the results of multiple measurements with various measurement conditions, keys or recipes. With this
proposed method, the measurement accuracy can be improved and we can enable a new knob for overlay control.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.