This will count as one of your downloads.
You will have access to both the presentation and article (if available).
Edge Placement Error (EPE) has been proposed to define the requirements of a patterning process. Many authors have created statistical models for EPE, and gathered statistical data for CD and overlay (OVL), to make predictions about future technology specifications1-5. This work makes the following contributions:
-
Emphasis on large amount (63K) of on-product measurements
-
Use of ANOVA table to assess the hypothesis that a contender process is better than a POR process To differentiate our work, we have used the stochastic variable IPFE (Interactive Pattern Fidelity Error), which is an indicator to quantify the quality of on-wafer edge placement accuracies in multi-patterning6. In our previous paper, we have studied how overlay, LCDU and pitch walk factor into the IPFE budget7. In this work, we focus on experimental verification of the expected relationships between LCDU, overlay and CD variation, applied to the case of SADP (block on spacer):
-
We re-confirm that population ‘blocks-on-gap’ have a worse IPFE performance than ‘block-on-core’
-
We determine experimental behavior of IPFE vs line CD, block CD, and overlay (w/o assumption for any model) From this exercise, we can conclude that this IPFE indicator is a robust metric for the managing quality of any integrated patterning scheme.
To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.
Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.
Tokyo Electron Limited has focused its efforts in scaling many laboratory demonstrations to 300 mm wafers. Additionally, we have recognized that the use of DSA requires specific design considerations to create robust layouts. To this end, we have discussed the development of a DSA ecosystem that will make DSA a viable technology for our industry, and we have partnered with numerous companies to aid in the development of the ecosystem. This presentation will focus on our continuing role in developing the equipment required for DSA implementation specifically discussing defectivity reduction on flows for making line-space and hole patterns, etch transfer of DSA patterns into substrates of interest, and integration of DSA processes into larger patterning schemes.
View contact details
No SPIE Account? Create one
