A method for using wet development in a directed self-assembly lithography (DSAL) application is reported. For the typical diblock copolymer poly(styrene-block-methyl methacrylate) (PS-b-PMMA), the PMMA area is removed by an oxygen plasma. However, the oxygen plasma has poor selectivity for the PS portion of the block polymer and etches it simultaneously. As a result, the thickness of the residual PS pattern is thinner than desired and creates a challenge for subsequent pattern transfer. A wet development technique is discussed which offers higher selectivity between the PMMA and PS blocks in the assembled pattern. Specifically, a method using a low pressure mercury lamp and conventional tetramethylammonium hydroxide (TMAH, 2.38%) developer is proposed. Using this method, DSA pattern formation is completed in a single track having coating, baking, exposure, and development modules.
The potentiality of line width roughness (LWR) reduction by ion implantation (I/I) in the extreme ultra violet (EUV)
lithography resist pattern was studied. The Argon ions were implanted to the Line-and-Space (L/S) pattern of EUV resist
with changing ion energy, dose and incident angle. The LWR and line width of 32 nm half-pitch L/S pattern was
evaluated after development, after I/I and after dry etching of the experimental thin hard mask beneath the resist pattern.
The LWR of 4.2 nm 3 σ, corresponding to the reduction of 1.6 nm, was obtained for resist after I/I with relatively low
energy condition of 1~5 keV. On the other hand, the best value of LWR after hard mask dry etching was 3.6 nm 3σ with I/I energy of 15 keV. It was found that preferable I/I condition for LWR reduction cannot be decided I/I alone but
should be optimized combined with etching.
We report wet development technique for directed self-assembly lithography pattern. For typical diblock copolymer,
poly (styrene-block-methyl methacrylate) (PS-b-PMMA), the PMMA area is removed by O2 plasma. However, O2 plasma attack also etches off PS area simultaneously. As a result, the thickness of residual PS pattern is thinner and it
causes degradation of PS mask performance. PS thickness loss in the device integration is not desirable as etching mask
role. In this work, we applied wet development technique which could be higher selectivity to keep PS film thickness
after pattern formation. Especially, we propose the method using low pressure mercury lamp and conventional TMAH
(2.38%) as developer. It is expected to accomplish pattern formation in one track with coating, baking, exposure and
development.
In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1)
for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the
printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered,
and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to
the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction
enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask
error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF)
to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with
the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy
(Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm
via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical
properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for
Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography
is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.
This paper reports the extracted risk issues on practical EUV resist processes and discusses verifications of them. The
risk issues were extracted with emphasis on critical dimension, defectivity and productivity for mass production EUV
resist processes. The authors verified these risk factors by utilizing available empirical knowledge. The authors found
that the micro loading effect of by-product in the resist development process was a key factor for CD uniformity. Also
discovered, was that high surface energy differences on the patterned wafers were a key factor for defectivity. As a result,
application of scan-dynamic development and dynamic scan rinse to EUV processes on a mass production level will
contribute greatly to CD and defect control as well as productivity.
Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication.
This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35
nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene
interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack
resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A
multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal-
2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased
corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical
proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm.
The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the
uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL
test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.
Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch
of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography
technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by
means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test
pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by
etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22-
nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on
yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer
process for device manufacture at the 22-nm node and beyond.
This work concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacturing based on accelerated development in critical areas, and the construction of a process liability (PL) test site that integrates results in these areas. Overall lithography performance is determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. The effect of flare on CD variation is a critical issue in EUVL, so flare is compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that take resist blur into account. Production readiness of EUVL based on the integration of results in these areas is evaluated by electrical tests on low-resistance tungsten wiring. We find the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.
This paper summarizes the development of EUV resists at Semiconductor Leading Edge Technologies (Selete): the
benchmarking results of more than 160 EUV resists from resist manufacturers using the small field exposure tool
(SFET) and the selection of the Selete standard resists (SSR) for the SFET. We discuss the current status of EUV
resist performance compared to the targets for 32-nm half-pitches (hp) concerning resist sensitivity, ultimate
resolution, and line-width-roughness (LWR). In addition we show the screening results of new resin materials.
EUV lithography performances of resist materials with different molecular weight of polymer were investigated. EUV
exposure experiment using a SFET at Selete clearly showed that line-width roughness (LWR) and 1:1 half-pitch (hp)
resolution were each improved using the polymers with middle and low molecular weights. These polymers showed high
dissolution contrast relative to polymer with high molecular weight. Mask linearity data also showed that the polymer
with low molecular weight gave a linear dependence on critical dimension (CD) against mask size down to hp 26 nm.
Thermal analysis of resist film revealed that thermal glass transition temperature (Tg) was dramatically decreased from
190 °C to 110 °C with decreasing molecular weight from high to low. In contrast with Tg which directly reflects
mobility of polymer, exposure latitude (EL) was increased from 12.3% to 14.5% at hp 32 nm by decreasing molecular
weight of polymer. Similarly, iso-dense bias was also improved by utilizing the low molecular weight polymer.
Combination of PAG-B with the low molecular weight polymer caused further improvement in mask linearity, EL, and
iso-dense bias at hp 32 nm, although LWR was rather increased.
KEYWORDS: Etching, Reactive ion etching, Extreme ultraviolet lithography, Silicon, Manufacturing, System on a chip, Photoresist processing, Scanning electron microscopy, Photomasks, Overlay metrology
Test chip manufacturing is an ongoing program at Selete in order to evaluate all elements of extreme ultraviolet
lithography (EUVL) such as mask, source, exposure tool, flare compensation, resist material, and pattern transfer
processes. One such test chip represents a back end of process - test elements group (BEP-TEG) which is a dual
damascene process with an overlay of 35nm-half pitch (hp). Pattern transfer process development for the BEP-TEG
manufacturing is investigated. The multi-stack films for pattern transfer are coated films only. The main items for
evaluation were resist thickness, necessity of bottom anti-refracting coat (BARC) between resist film and spin on glass
(SOG) film, and the BARC material itself and its thickness. The BARC material was evaluated from the stand points of
outgassing, etching rate, resist pattern collapse, and resist pattern profiles. Working with resultant multi-stack films,
35nm-hp dense line patterns and 70nm-pitch dense contact-hole patterns were successfully transferred to low-k film.
This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on
accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in
these areas. The overall lithography performance was determined from the performance of the exposure tool, the
printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction
technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33
mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus,
the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation
of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on
CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the
projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an
electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal
wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of
EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten
wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were
found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We
found the PL test site to be very useful for determining where further improvements need to be made and for evaluating
the production readiness of EUVL.
The main challenge facing the implementation of EUV resist and processing has been concurrent achievement of high
sensitivity, high resolution, and low line width roughness (LWR). In order to improve the performance of EUV resist,
Selete is actively pursuing its benchmarking. The results from this benchmarking were found to be as follows: Esize
improved with the increasing capability of EUV pattern exposure. Sensitivity improved during this year. Resolution is
found to be almost sufficient for 32-nm half-pitch (hp), but not quite good enough for 22-nm hp. Resist blur of the resist,
which marked good score in benchmarking, is found to be 10nm to 11nm. LWR is still far from its target value.
Line width roughness (LWR) reduction is a critical issue for low k1 ArF immersion lithography. Various approaches
such as materials, exposure technology and the track process have been performed for LWR reduction during
lithography process.
It was reported that the post-development bake process had good performance for LWR reduction (1). However, the
post-development bake process induced large CD change owing to the degradation of large isolated resist pattern.
Therefore post-development process with small iso-dense bias is required in low k1 ArF immersion lithography.
The resist smoothing process is one of the candidates for LWR reduction with small iso-dense bias. This method
whereby the resist pattern surface is partially melted in organic-solvent atmosphere was shown to have a significant
LWR reduction effect on resist patterns. This paper reports on the application of the resist smoothing process to the
ArF immersion resist pattern after development. It was found that the resist smoothing process was effective to reduce
LWR for ArF immersion resist. As a result of LWR trace from after development to after the hard mask etching process,
the effect of LWR reduction with the resist smoothing process continued after the hard mask etching process.
Furthermore CD change of large isolated patterns with the smoothing process was smaller than in the case of post-development
bake process. We confirmed that the resist smoothing process is an effective method for decreasing LWR
in ArF immersion lithography.
The main development issue regarding EUV resist has been how to concurrently achieve high sensitivity, high resolution, and low line width roughness (LWR). This paper describes the current status of EUV resist development at Selete with a small field exposure tool (SFET). Selete standard resist 2 (SSR2) can simultaneously resolve 26-nm dense and isolated lines with the SFET. Our top data for resolution with annular illumination shows a 25-nm half-pitch. In evaluating resist performance, resist blur should be estimated separately from exposure tool fluctuations. By considering the aberration, flare, and actual illumination shape, resist blur can be estimated more accurately. We estimate the resist blur for SSR2 to be between 9.5 and 10.4 nm as sigma of the Gaussian convolution. We also present benchmarking results for suppliers' samples. Though sensitivity has been improved somewhat in some resists, further improvement is necessary. Further reduction of LWR is especially needed.
In immersion lithography, it is necessary that the surface of wafer has high hydrohybicity in order to prevent the residue of immersion fluid, i.e. pure water, that cause watermark defect. Usage of a cover material film over the resist film is effective to consistent with high hydrohybicity of the surface and high performance of resist film. But it was problem that much pattern deformation defects was observed with the use of an alkali-soluble type cover material film and an immersion exposure tool. As a result of the examination, it was identified that the fraction of film which caused the pattern deformation in the area of several micrometers were the fraction of the cover material. And the fractions of cover coat material were oriented in the coating defects of the cover material film and in the film peeling after scan of the immersion nozzle at the wafer bevel. The coating defects were improved with the chemical of the cover material. An adhesion process was effective to prevent the film peeling of cover material.
KEYWORDS: Scanning electron microscopy, Semiconducting wafers, Digital watermarking, Immersion lithography, Silicon, Photoresist processing, Thin film coatings, Coating, Liquids, Water
In the liquid immersion lithography, uses of the cover material (C/M) films were discussed to reduce elution of resist components to fluid. With fluctuation of exposure tool or resist process, it is possible to remain of waterdrop on the wafer and watermark (W/M) will be made. The investigation of influence of the W/M on resist patterns, formation process of W/M, and reduction of pattern defect due to W/M will be discussed. Resist patterns within and around the intentionally made W/M were observed in three cases, which were without C/M, TOK TSP-3A and alkali-soluble C/M. In all C/M cases, pattern defect were T-topped shapes. Reduction of pattern defects due to waterdrop was examined. It was found that remained waterdrop made defect. It should be required to remove waterdrop before drying, and/or to remove the defect due to waterdrop. But new dry technique and/or unit will be need for making no W/M. It was examined that the observation of waterdrop through the drying step and simulative reproduction of experiment in order to understand the formation mechanism of W/M. If maximum drying time of waterdrop using immersion exposure tool is estimated 90 seconds, the watermark of which volume and diameter are less than 0.02 uL and 350um will be dried and will make pattern defect. The threshold will be large with wafer speed become faster. From result and speculations in this work, it is considered that it will be difficult to development C/M as single film, which makes no pattern defects due to remained waterdrop.
“Dose-MEF” was measured on ArF and KrF resists. The “dose-MEF” is very important factor for mask making spec. Conventional lithography simulation such as “Diffused aerial image simulation” does not predict the ArF experimental value precisely. In order to explain the dose-MEF of ArF resist, we introduce intensity biasing. The intensity biasing is caused by flare of exposure tool and another mechanism. The intensity biasing reduces the dose-MEF. Small dose-MEF leads to the relaxed mask spec.
KEYWORDS: Finite element methods, Photomasks, Semiconducting wafers, Data modeling, Critical dimension metrology, Scanning electron microscopy, Diffraction, Temperature metrology, Solids, Scanners
An Illumination intensity distribution of an exposure tool varies CD in simulation. In order to obtain reliable resist parameters, we studied the influence of the illumination intensity distribution in tuning the resist parameters and the accuracy of the simulation using the tuned resist parameters under different illumination conditions from in tuning. We tuned resist parameters with two models of illumination intensity to experimental FEM data. One model, "Nominal", was assumed to be uniform intensity and a nominal shape of an exposure tool. Another model, "Measured", was measured illumination intensity distribution with grating-pinhole mask.
Under the same illumination condition to tuning, RMS of CD difference between experiment and simulation using "Measured" in tuning and simulation was 0.7nm smaller than that using "Nominal". But under the different illumination condition from tuning, RMS using "Measured" was 1.4 - 1.6nm smaller in total of 1D-pattern than that using "Nominal". In the specific pattern RMS using "Measured" was rather smaller than RMS using "Nominal". These results indicate that, in order to gain accurate simulation result, the accurate illumination intensity distributions is need in tuning and simulation.
If using "Nominal" in tuning and in simulation, CD difference between experiment and simulation will enlarge in fine patterns.
We investigated dependence of ArF resist on Exposed Area Ratio (EAR). Because it can be one of the CD variation factor and it is difficult to correct by OPC. Acrylate polymer based resist showed dependence on EAR. At low EAR, resist showed T-top profile and its CD became large. It could be considered that the profile change was caused by acid evaporation and re-sticking. Resist profile simulation indicated that CD variation appeared at only low EAR. To decreasing the effect of acid evaporation and re-sticking, we tried to increase the amount of acid evaporation by increasing PAB temperature. CD variation by EAR was decreased with increasing PAB temperature.
We investigated resist profile dependence on Exposed Area Ratio (EAR). Using high activation type chemically amplified positive resist, profile changed from T-top to rounded profile with increasing EAR. We thought that this profile change was caused by acid evaporation and re- sticking. To estimate the effect of re-sticking acid, we performed resist sandwich tests. We measured resist thickness loss after PEB and observed resist profile change caused by re-sticking acid. The results thereby obtained suggest the model we propose. To reduce acid evaporation and re-sticking, we tried to use an overcoat layer. The overcoat layer was found to reduce acid evaporation and be useful for reducing resist profile dependence on EAR.
Aerial image contrast dependence of line edge roughness (LER) in 130 nm equal line and space resist patterns was investigated using chemically amplified resists on organic bottom antireflective coatings both for KrF imaging and for ArF imaging. The chemically amplified ArF resist exhibiting high transparency both at 248 nm and at 193 nm was found to resolve 130 nm equal line and space resist patterns both on the KrF imaging systems and on the ArF imaging system using an identical binary mask set. Average roughness measurement data derived from top-down scanning electron microscopic images of the 130 nm equal line and space resist patterns indicated that the LER decreased with increasing the aerial image contrast, varying with the wavelengths of illumination light sources and the illumination conditions. It was, however, found that the LER in the chemically amplified resist optimized for the ArF imaging system was 1.9 - 2.3 times larger than those in the chemically amplified resists optimized for the KrF imaging systems, in spite of the fact that the aerial image contrast of the ArF imaging system was 1.5 - 2.5 times higher than those of the KrF imaging systems.
Recently, resist edge roughness with reducing pattern size has become a serious problem. We investigated the roughness of chemically amplified, positive-tone resists, experimentally. To reduce the roughness, we added a quencher with strong basicity to the resist, and observed sub quarter micron nested lines. As a result, the roughness was improved with increasing the quencher concentration, especially in 0.15 micrometers nested line patterns. Adding quencher was not too much effective for the larger size patterns. The acid concentration in resist was increased by adding quencher, because the nominal dose became large by that. It was also indicated experimentally that generated acid concentration at pattern edge was nearly equal to that of quencher at nominal dose. The nominal dose was determined by quencher concentration. We defined effective acid concentration as remaining acid concentration after quenching. This effective acid concentration increased with increasing quencher concentration too. The roughness seemed to be generated when effective acid concentration profile was lowered. It is indicated that the resist edge roughness with reducing pattern size can be expected from its effective acid concentration profile.
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