Dr. Shumay Shang Profile

Dr. Shumay Shang

Product Manager at Siemens EDA

SPIE Involvement:

Author

Area of Expertise:

Photolithography , IC manufacturing Process , DFM , OPC/ORC/RET , EDA , Physical Chemistry

Publications (29)

Proceedings Article | 9 April 2024 Paper

Principal components and optimal feature vectors of EUVL stochastic variability: applications of Karhunen-Loève expansion to efficient estimation of stochastic failure probabilities and stochastic metrics

Azat Latypov, Chih-I Wei, Shumay Shang, Germain Fenger

Proceedings Volume 12957, 129571D (2024) https://doi.org/10.1117/12.3011090

KEYWORDS: Stochastic processes, Extreme ultraviolet lithography, Covariance, Failure analysis, Monte Carlo methods, Statistical analysis, Principal component analysis, Photoresist processing, 3D modeling, Extreme ultraviolet

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Proceedings Article | 21 November 2023 Presentation + Paper

Machine learning assisted effective OPC verification hotspot capture

Lianghong Yin, Marko Chew, Shumay Shang, Le Hong, Fan Jiang, Ilhami Torunoglu

Proceedings Volume 12751, 127510W (2023) https://doi.org/10.1117/12.2687752

KEYWORDS: Optical proximity correction, Image classification, Design and modelling, Machine learning, Data modeling, Critical dimension metrology, Tunable filters, Scanning electron microscopy, Inspection

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Proceedings Article | 28 April 2023 Poster + Paper

EUV SRAFs printing modeling and verification in 2D hole array

Ling Ee Tan, Chih-I Wei, Lianghoon Yin, Azat Latypov, Shuling Wang, Satya Sriram, Prakash Deep, Farruh Shahidi, Shumay Shang, Germain Fenger, Le Hong, Werner Gillijns

Proceedings Volume 12494, 1249417 (2023) https://doi.org/10.1117/12.2658320

KEYWORDS: SRAF, Printing, Stochastic processes, Modeling, Semiconducting wafers, Scanning electron microscopy, Extreme ultraviolet, Design and modelling, Data modeling, Photomasks

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Proceedings Article | 16 September 2022 Paper

EUV SRAFs printing modeling with bright field mask

Chih-I Wei, Azat Latypov, Shuling Wang, Satya Sriram, Prakash Deep, Yunfei Deng, Ethan Maguire, Shumay Shang, Germain Fenger, Werner Gillijns

Proceedings Volume 12325, 1232506 (2022) https://doi.org/10.1117/12.2640532

KEYWORDS: SRAF, Semiconducting wafers, Stochastic processes, Data modeling, Scanning electron microscopy, Photomasks, Extreme ultraviolet, Calibration, Line width roughness

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Proceedings Article | 26 May 2022 Presentation + Paper

Machine learning based error classification for curvilinear designs

Lianghong Yin, Shumay Shang, Fan Jiang, Le Hong, Robin Chia, Juli Opitz, Paul Adam, Ian Stobert, Yee-Wee Koh

Proceedings Volume 12052, 120520A (2022) https://doi.org/10.1117/12.2613933

KEYWORDS: Tolerancing, Silicon photonics, Optical proximity correction, Machine learning, Silicon, Vector spaces, Photomasks, Electronic design automation, Data modeling, Waveguides

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Curvilinear design layout is becoming increasingly prevalent in semiconductor manufacturing industry. One of the applications is Silicon Photonics. Silicon Photonics design layout requires the use of curvilinear shapes to minimize the loss of signal strength. Other applications include curvilinear Mask Proximity Correction (CL MPC), verification (CL MPCV), Mask Rule Checking (CL MRC), microelectromechanical system (MEMS), on-chip metasurface optics, etc. Curvilinear design layout poses new challenges to computational lithography tools that were developed mainly to handle Manhattan geometries. It has been found that the geometry-based error classification used in the Optical Proximity Correction (OPC) verification flow has its limitations to support curvilinear designs. In this paper, we present our innovative work of using Siemens EDA Calibre® OPCVerify Machine Learning (ML) Classify technology to classify error markers in the feature vector space instead of traditional pattern’s vertices and edges geometries. There are five steps in our OPCVerify ML Classify: 1. use primary checks to output error markers, 2. design features and create feature vector kernels, 3. collect feature vectors at error marker locations, 4. prepare patterns with pre-knowledge of desired classify guidance and train ML model, and 5. apply ML classify model to classify error markers on full layout in the feature vector space. In our experiments, ML Classify is successful in classifying OPC verification error markers in curvilinear designs. A drawn silicon photonics layout with 837,072 raw error locations has demonstrated our ML Classify tool’s capability to reduce the unique class count from 221,085 based on conventional geometry-based classify approach down to 51. We also developed further sub-classify feature which provides options to further sub-classify results by edge types, convex, concave, or straight line, and by polygon’s internal width and external space to neighboring polygons. The 51 unique class count becomes 2493 after the further sub-classify process. This methodology is not only good for silicon photonics application, but also good for other curvilinear photomask applications, like CL MPCV, MEMS, on-chip metasurface optics, and in general even Manhattan designs.

Proceedings Article | 22 February 2021 Presentation + Paper

Gaussian random field EUV stochastic models, their generalizations and lithographically meaningful stochastic metrics

Azat Latypov, Gurdaman Khaira, Germain Fenger, Shuling Wang, Marko Chew, Shumay Shang

Proceedings Volume 11609, 1160917 (2021) https://doi.org/10.1117/12.2583792

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Proceedings Article | 15 October 2020 Presentation + Paper

MRC for curvilinear mask shapes

Ingo Bork, Alexander Tritchkov, Shumay Shang, Evgueni Levine, Mary Zuo

Proceedings Volume 11518, 115180R (2020) https://doi.org/10.1117/12.2575474

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Proceedings Article | 20 March 2020 Presentation + Paper

Stochastic model prediction of pattern-failure

Sophie (Hyejin) Jin, John Sturtevant, Shumay Shang, Lianghong Yin, Kevin Ahi

Proceedings Volume 11325, 113250G (2020) https://doi.org/10.1117/12.2553235

KEYWORDS: Stochastic processes, SRAF, Failure analysis, Printing, Extreme ultraviolet, Line edge roughness, Photoresist materials, Semiconducting wafers, Extreme ultraviolet lithography, Photons

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It has long been observed that certain pattern-failure phenomena manifest in an apparent random manner on wafer. Thus for a design pattern featuring multiple identical repeats in identical surrounding environments, some locations will at certain processing conditions result in failure, whereas identical patterns in direct proximity might not exhibit failure. Two examples of such are sub-resolution assist features (SRAF) printing and aspect-ratio dependent pattern collapse. SRAFs are of course designed to not print on the wafer, but it is observed that when SRAFs of a certain size or proximity to the main feature, at a specific dose and focus condition, are first observed to print on wafer, they do so in a random manner. The clearest demonstration of this is for a simple grating pattern with long running simple 1D lines interspersed with uniformly sized SRAF on the mask. Depending upon the resist system polarity, it is common to see splotches of partially printed SRAF dimples in the photoresist, or residual scum of photoresist appearing randomly along the length of the SRAM location. This behavior can be ascribed to the cumulative stochastic effects of exposure, PEB, and develop. A more complex phenomenon is pattern-collapse, which has been thoroughly researched and shown to be related to non-uniform capillary forces acting upon the newly developed photoresist pattern as well as the profile and bottom CD of those patterns. The result can again be an apparent randomness to the toppling of patterns which are nominally identical, especially when layout and process conditions are right at the onset of failure observation. Early experimental work in characterizing these two phenomena were often based on simple SEM image analysis, and demonstrated perhaps parts per thousand sensitivity. More sophisticated optical imaging techniques such as E-beam inspection can achieve perhaps parts per million sensitivity. With the advent of EUV lithography, there has been increased attention on stochastic effects, owing to the relatively few number of photons involved in the exposure of a single pattern. The result has been improved experimental methodologies for characterizing stochastic phenomena such as micropinching or micro-bridging, as well as improved simulation of these random behaviors. For 7 nm and below, the required sensitivity to protect yield is less than parts per billion. In this work, we report on the use of stochastic models to quantify the prediction of SRAF printing and pattern-collapse through the process window. Simple grating patterns with variable sized single SRAFs are used for characterization of the failure rate expressed in terms of percent of total SRAF mask layout area in the design block. For pattern collapse simulation, an array of photoresist posts are utilized, and as a proxy for pattern collapse, we use bottom CD area calculated from the randomized simulated contour. We use a range of different stochastic models to represent variable degrees of stochastic contribution and show the impact on main feature line edge roughness (LER) as well as pattern failure. Examples are shown for both EUV and 193i cases, and it is highlighted that stochastic failure is not relegated solely to EUV.

Proceedings Article | 20 March 2020 Presentation + Paper

Real-time full-wafer design-based inter-layer virtual metrology

Lianghong Yin, John Sturtevant, Alberto Lopez Gomez, Shumay Shang, Young Chang Kim, Kostas Adam, Marko Chew, Abhinandan Nath, Boris Habets, Manuela Gutsch, Philip Groeger

Proceedings Volume 11325, 1132507 (2020) https://doi.org/10.1117/12.2551082

KEYWORDS: Semiconducting wafers, Data modeling, Overlay metrology, Metals, Metrology, Critical dimension metrology, Databases, Inspection, Computer simulations, Scanners

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Proceedings Article | 20 March 2019 Presentation + Paper

Process window-based feature and die failure rate prediction

John Sturtevant, Lianghong Yin, Young Chang Kim, Shumay Shang, Andrew Burbine, Chris Clifford, Kostas Adam

Proceedings Volume 10962, 109620B (2019) https://doi.org/10.1117/12.2516101

KEYWORDS: Failure analysis, Critical dimension metrology, Lithography, Logic, Manufacturing, Photomasks, Error analysis, Stochastic processes, Visualization, Optical proximity correction

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Proceedings Article | 28 March 2018 Presentation + Paper

Combinational optical rule check on hotspot detection

Alexander Wei, Shaowen Gao, Yuansheng Ma, Shumay Shang, Yuyang Sun, Rui Wu, Lianghong Yin, Hongxin Zhang

Proceedings Volume 10588, 105880K (2018) https://doi.org/10.1117/12.2297425

KEYWORDS: Optical proximity correction, Failure analysis, Semiconducting wafers, Calibration, Data modeling, Photomasks, Inspection, Optics manufacturing, Bridges, Finite element methods

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Proceedings Article | 19 March 2018 Presentation + Paper

Impact of aberrations in EUV lithography: metal to via edge placement control

Lianghong Yin, Ananthan Raghunathan, Germain Fenger, Shumay Shang, Neal Lafferty, John Sturtevant

Proceedings Volume 10583, 105830Q (2018) https://doi.org/10.1117/12.2299872

KEYWORDS: Metals, Optical proximity correction, Scanners, Extreme ultraviolet lithography, Manufacturing, Overlay metrology, Bridges, Optical lithography, Logic, Photomasks

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Proceedings Article | 23 October 2015 Paper

Characterization and mitigation of relative edge placement errors (rEPE) in full-chip computational lithography

John Sturtevant, Rachit Gupta, Shumay Shang, Vlad Liubich, James Word

Proceedings Volume 9635, 963505 (2015) https://doi.org/10.1117/12.2196634

KEYWORDS: Metals, Optical lithography, Overlay metrology, Critical dimension metrology, Manufacturing, Monochromatic aberrations, Photomasks, Double patterning technology, Optical proximity correction, Computational lithography

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Edge placement error (EPE) was a term initially introduced to describe the difference between predicted pattern contour edge and the design target. Strictly speaking this quantity is not directly measurable in the fab, and furthermore it is not ultimately the most important metric for chip yield. What is of vital importance is the relative EPE (rEPE) between different design layers, and in the era of multi-patterning, the different constituent mask sublayers for a single design layer. There has always been a strong emphasis on measurement and control of misalignment between design layers, and the progress in this realm has been remarkable, spurned in part at least by the proliferation of multi-patterning which reduces the available overlay budget by introducing a coupling of alignment and CD errors for the target layer.

In-line CD and overlay metrology specifications are typically established by starting with design rules and making certain assumptions about error distributions which might be encountered in manufacturing. Lot disposition criteria in photo metrology (rework or pass to etch) are set assuming worst case assumptions for CD and overlay respectively. For example poly to active overlay specs start with poly endcap design rules and make assumptions about active and poly lot average and across lot CDs, and incorporate general knowledge about poly line end rounding to ensure that leakage current is maintained within specification. This worst case guard banding does not consider specific chip designs, however and as we have previously shown full-chip simulation can elucidate the most critical "hot spots" for interlayer process variability comprehending the two-layer CD and misalignment process window. It was shown that there can be differences in X versus Y misalignment process windows as well as positive versus negative directional misalignment process windows and that such design specific information might be leveraged for manufacturing disposition and control schemes.

This paper will further investigate examples of via-metal model-based analysis of CD and overlay errors. We will investigate both single patterning and double patterning. For single patterning, we show the advantage of contour to contour simulation over contour to target simulation, and how the addition of aberrations in the optical models can provide a more realistic PW window for edge placement errors. For double patterning, the interaction of 4 layer CD and misalignment errors is very complex, but we illustrate that not only can full-chip verification identify potential rEPE hotspots, the OPC engine can act to mitigate such hotspots and enlarge the overall combined CD-overlay rEPE process window.

Proceedings Article | 18 March 2015 Paper

Full chip two-layer CD and overlay process window analysis

Rachit Gupta, Shumay Shang, John Sturtevant

Proceedings Volume 9427, 94270H (2015) https://doi.org/10.1117/12.2086368

KEYWORDS: Metals, Overlay metrology, Error analysis, Manufacturing, Photomasks, Model-based design, Critical dimension metrology, Etching, Semiconducting wafers, Yield improvement

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Proceedings Article | 12 April 2013 Paper

Model-based stitching and inter-mask bridge prevention for double patterning lithography

Guillaume Landié, Jean-Noel Pena, Serguey Postnikov, James Word, Shumay Shang, Fahd Chaoui, Emek Yesilada, Catherine Martinelli

Proceedings Volume 8683, 868316 (2013) https://doi.org/10.1117/12.2011494

KEYWORDS: Optical proximity correction, Photomasks, Double patterning technology, Bridges, Lithography, Etching, Metals, Visualization, Manufacturing, Optical lithography

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Proceedings Article | 30 October 2007 Paper

Etch proximity correction by integrated model-based retargeting and OPC flow

Shumay Shang, Yuri Granik, Martin Niehoff

Proceedings Volume 6730, 67302G (2007) https://doi.org/10.1117/12.746773

KEYWORDS: Etching, Optical proximity correction, Model-based design, Integrated modeling, Calibration, Optical calibration, Visibility, Photomasks, Visualization, Photoresist processing

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Proceedings Article | 21 March 2007 Paper

Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability

Travis Brist, Le Hong, Ayman Yehia, Tamer Tawfik, Shumay Shang, Kyohei Sakajiri, John Sturtevant

Proceedings Volume 6521, 65211L (2007) https://doi.org/10.1117/12.712748

KEYWORDS: SRAF, Optical proximity correction, Critical dimension metrology, Manufacturing, Photomasks, Model-based design, Antimony, Design for manufacturability, Optimization (mathematics), Resolution enhancement technologies

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Proceedings Article | 20 October 2006 Paper

Minimizing yield-loss risks through post-OPC verification

Ching-Heng Wang, Qingwei Liu, Liguo Zhang, Gen-Sheng Gao, Travis Brist, Tom Donnelly, Shumay Shang

Proceedings Volume 6349, 63494N (2006) https://doi.org/10.1117/12.686585

KEYWORDS: Manufacturing, Optical proximity correction, Lithography, Photomasks, Semiconducting wafers, Critical dimension metrology, Scanning electron microscopy, Semiconductor manufacturing, Reticles, Silicon

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Proceedings Article | 20 October 2006 Paper

On objectives and algorithms of inverse methods in microlithography

Yuri Granik, Kyohei Sakajiri, Shumay Shang

Proceedings Volume 6349, 63494R (2006) https://doi.org/10.1117/12.691810

KEYWORDS: SRAF, Photomasks, Detection and tracking algorithms, Optical lithography, Image processing, Mask making, Lithography, Optical calibration, System on a chip, Manufacturing

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Proceedings Article | 20 May 2006 Paper

Model-based insertion of assist features using pixel inversion method: implementation in 65 nm node

Chi-Yuan Hung, Qingwei Liu, Kyohei Sakajiri, Shumay Shang, Yuri Granik

Proceedings Volume 6283, 62832Y (2006) https://doi.org/10.1117/12.681816

KEYWORDS: SRAF, Photomasks, Model-based design, Optical proximity correction, Metals, Lithography, Semiconducting wafers, Logic, Mask making, Inspection

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Proceedings Article | 16 March 2006 Paper

The influence of calibration pattern coverage for lumped parameter resist models on OPC convergence

Martin Niehoff, Shumay Shang, Olivier Toublan

Proceedings Volume 6156, 615619 (2006) https://doi.org/10.1117/12.657536

KEYWORDS: Calibration, Optical proximity correction, Data modeling, Visualization, Printing, Optical simulations, Feature extraction, Process modeling, Metals, Scanning electron microscopy

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Proceedings Article | 9 November 2005 Paper

Integrated post tape outflow for fast design to mask turn-around time

Chi-Yuan Hung, Qingwei Liu, Liguo Zhang, Shumay Shang, George Bailey, Andrew Jost, Travis Brist

Proceedings Volume 5992, 599251 (2005) https://doi.org/10.1117/12.629042

KEYWORDS: Optical proximity correction, Photomasks, Data modeling, Back end of line, Semiconducting wafers, Visualization, Databases, Scanning electron microscopy, Data integration, Metals

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Proceedings Article | 8 November 2005 Paper

Model-based insertion and optimization of assist features with application to contact layers

Shumay Shang, Yuri Granik, Lisa Swallow, Li-guo Zhang, Travis Brist, Andres Torres, Chi-Yuan Hung, Qingwei Liu

Proceedings Volume 5992, 59921Y (2005) https://doi.org/10.1117/12.632345

KEYWORDS: SRAF, Photomasks, Model-based design, Source mask optimization, Optical proximity correction, Critical dimension metrology, Optimization (mathematics), Lithography, Semiconducting wafers, Scanning electron microscopy

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Proceedings Article | 28 June 2005 Paper

Lithography process related OPC development and verification demonstration on a sub-90nm poly layer

Chi-Yuan Hung, Qingwei Liu, Liguo Zhang, Shumay Shang, Andrew Jost

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617194

KEYWORDS: Process modeling, Optical proximity correction, Data modeling, Photomasks, Semiconducting wafers, Scanning electron microscopy, Calibration, Lithography, Wafer-level optics, Visualization

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Proceedings Article | 12 May 2005 Paper

High accuracy 65nm OPC verification: full process window model vs. critical failure ORC

Amandine Borjon, Jerome Belledent, Shumay Shang, Olivier Toublan, Corinne Miramond, Kyle Patterson, Kevin Lucas, Christophe Couderc, Yves Rody, Frank Sundermann, Jean-Christophe Urbani, Stanislas Baron, Yorick Trouiller, Patrick Schiavone

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.600471

KEYWORDS: Data modeling, Optical proximity correction, Calibration, Printing, Optical lithography, Scanning electron microscopy, Process modeling, 3D modeling, Lithography, Photomasks

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It is becoming more and more difficult to ensure robust patterning after OPC due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. The techniques of Mask Rule Checking (MRC) and Optical Rule Checking (ORC) have become mandatory tools for ensuring that OPC delivers robust patterning. However the first method relies on geometrical checks and the second one is based on a model built at best process conditions. Thus those techniques do not have the ability to address all potential printing errors throughout the process window (PW). To address this issue, a technique known as Critical Failure ORC (CFORC) was introduced that uses optical parameters from aerial image simulations. In CFORC, a numerical model is used to correlate these optical parameters with experimental data taken throughout the process window to predict printing errors. This method has proven its efficiency for detecting potential printing issues through the entire process window [1]. However this analytical method is based on optical parameters extracted via an optical model built at single process conditions. It is reasonable to expect that a verification method involving optical models built from several points throughout PW would provide more accurate predictions of printing errors for complex features. To verify this approach, compact optical models similar to those used for standard OPC were built and calibrated with experimental data measured at the PW limits. This model is then applied to various test patterns to predict potential printing errors. In this paper, a comparison between these two approaches is presented for the poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two techniques are compared with experimental results. The details of implementing these two techniques on full product layouts are also included in this study.

Proceedings Article | 27 January 2005 Paper

Lithography yield enhancement through optical rule checking

James Word, J. Andres Torres, Thomas Roessler, Neal Lafferty, Shumay Shang

Proceedings Volume 5645, (2005) https://doi.org/10.1117/12.577609

KEYWORDS: Printing, Photomasks, Calibration, Lithography, Optical proximity correction, Scanning electron microscopy, Logic, Image processing, Data modeling, Process modeling

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Proceedings Article | 6 December 2004 Paper

MEEF-based mask inspection

Wilhelm Maurer, James Word, Steffen Schulze, Shumay Shang

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569330

KEYWORDS: Photomasks, Inspection, Optical proximity correction, Semiconducting wafers, SRAF, Printing, Lithography, Resolution enhancement technologies, Data modeling, Manufacturing

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Proceedings Article | 28 May 2004 Paper

Critical failure ORC: application to the 90-nm and 65-nm nodes

Jerome Belledent, Shumay Shang, Yorick Trouiller, Corinne Miramond, Kyle Patterson, Olivier Toublan, Christophe Couderc, Frank Sundermann, Yves Rody

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.537190

KEYWORDS: Optical proximity correction, Data modeling, Calibration, Printing, Visualization, Failure analysis, Bridges, Scattering, Image processing, Semiconducting wafers

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Proceedings Article | 26 June 2003 Paper

Failure prediction across process window for robust OPC

Shumay Shang, Yuri Granik, Nicolas Cobb, Wilhelm Maurer, Yuping Cui, Lars Liebmann, James Oberschmidt, Rama Singh, Ben Vampatella

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485478

KEYWORDS: Optical proximity correction, Data modeling, Printing, Image processing, Visualization, Calibration, Binary data, Solids, Failure analysis, Process modeling

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Showing 5 of 29 publications

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